riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-05-23	processor_t unfriends gdbserver_t.	Tim Newsome	6	-15/+34
2016-05-23	Correctly read PC on halt.	Tim Newsome	2	-11/+23
2016-05-23	Fix store to clear debug interrupt.	Tim Newsome	4	-2/+20
2016-05-23	Add debug_module bus device.	Tim Newsome	18	-58/+259
2016-05-23	ROM -> RAM -> ROM, waiting for debug int.	Tim Newsome	5	-2/+39
2016-05-23	Make sure to translate Debug RAM addresses also.	Tim Newsome	2	-2/+6
2016-05-23	Jump to the correct (temporary) Debug RAM address.	Tim Newsome	2	-6/+7
2016-05-23	Clean up how Debug ROM is included.	Tim Newsome	6	-8/+6
2016-05-23	Can jump to and execute Debug ROM.	Tim Newsome	9	-7/+25
2016-05-23	Check in compiled debug ROM.	Tim Newsome	2	-3/+24
2016-05-23	When gdb connects, jump to Debug ROM and segfault.	Tim Newsome	5	-11/+17
2016-05-23	Add debug rom code.	Tim Newsome	3	-0/+133
2016-05-23	Gutting direct-access gdb.	Tim Newsome	6	-40/+24
2016-05-23	Add writing to DCSR, DPC, DSCRATCH.	Tim Newsome	3	-0/+59
2016-05-23	Actually run the ebreak test.	Tim Newsome	1	-1/+2
2016-05-23	Only halt on ebreak if a debugger is attached.	Tim Newsome	3	-5/+12
2016-05-23	Test ebreak without gdb.	Tim Newsome	3	-6/+42
2016-05-23	Document attaching with gdb.	Tim Newsome	1	-4/+75
2016-05-23	Add --gdb-port	Tim Newsome	6	-34/+52
2016-05-23	Do a better job checking CSR functionality.	Tim Newsome	3	-5/+21
2016-05-23	Rename gdbserver-smoke.py to gdbserver.py.	Tim Newsome	2	-1/+1
2016-05-23	Test 'info registers all' as well as 'info all-registers'	Tim Newsome	1	-4/+6
2016-05-23	Minor cleanup.	Tim Newsome	2	-4/+4
2016-05-23	Update regnum handling to match gdb CSR changes.	Tim Newsome	3	-126/+58
2016-05-23	Forgot to add this source.	Tim Newsome	1	-0/+42
2016-05-23	Treat warnings as errors.	Tim Newsome	1	-2/+2
2016-05-23	Implement register writes.	Tim Newsome	4	-12/+118
2016-05-23	Properly clean up spike.	Tim Newsome	2	-2/+3
2016-05-23	Implement reading of CSRs.	Tim Newsome	3	-25/+132
2016-05-23	Add some tests that pass and test something.	Tim Newsome	5	-4/+126
2016-05-23	Flush icache when using swbps and report to gdb.	Tim Newsome	7	-15/+89
2016-05-23	Add very basic 'make check'.	Tim Newsome	1	-2/+14
2016-05-23	Make 'make check' not hang forever.	Tim Newsome	1	-1/+1
2016-05-23	Software breakpoints seem to work.	Tim Newsome	4	-13/+102
2016-05-23	Rewrite GPL'd code from OpenOCD.	Tim Newsome	1	-34/+17
2016-05-23	Looks like single step works.	Tim Newsome	5	-7/+60
2016-05-23	Add -H to start halted.	Tim Newsome	4	-5/+11
2016-05-23	Implement binary memory write.	Tim Newsome	2	-31/+86
2016-05-23	Now you can halt/continue from gdb.	Tim Newsome	5	-5/+60
2016-05-23	Register read looks sane now.	Tim Newsome	2	-8/+75
2016-05-23	gdb can now read spike memory.	Tim Newsome	5	-23/+97
2016-05-23	Hack to the point where gdb reads a register.	Tim Newsome	2	-28/+134
2016-05-23	Listen on a socket for gdb to connect to.	Tim Newsome	6	-0/+332
2016-05-22	Allow delegation of device interrupts	Andrew Waterman	2	-4/+7
2016-05-21	htif: catch proper store exception (#44)	Garret Kelly	1	-1/+1
2016-05-21	Some bugfixes for CSR reading and setting FS for fflags updates (#43)	Andy Wright	5	-9/+24
2016-05-19	Merge pull request #42 from csail-csg/master	Tim Newsome	1	-1/+0
2016-05-19	Removed devicetree.h from riscv.mk.in since it no longer exists	acw1251	1	-1/+0
2016-05-18	Added missing header files to riscv.mk.in	acw1251	1	-0/+3
2016-05-02	Add back IPI support	Andrew Waterman	2	-21/+22