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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-05-02 16:28:51 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-05-02 16:28:51 -0700 |
commit | 0d084d5686a72221237c26c576c793d1f6417816 (patch) | |
tree | 9c2e7f01b2db91b195acefaaf94c83db7b00221d | |
parent | 64fd5f375c11694d4093837b10f6bdd7c8b8db7f (diff) | |
download | riscv-isa-sim-0d084d5686a72221237c26c576c793d1f6417816.zip riscv-isa-sim-0d084d5686a72221237c26c576c793d1f6417816.tar.gz riscv-isa-sim-0d084d5686a72221237c26c576c793d1f6417816.tar.bz2 |
Add back IPI support
-rw-r--r-- | riscv/processor.cc | 25 | ||||
-rw-r--r-- | riscv/sim.cc | 18 |
2 files changed, 22 insertions, 21 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8714b97..ada5cd7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -523,23 +523,20 @@ void processor_t::register_base_instructions() bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) { - try { - auto res = get_csr(addr / (max_xlen / 8)); - memcpy(bytes, &res, len); - return true; - } catch (trap_illegal_instruction& t) { - return false; - } + return false; } bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) { - try { - reg_t value = 0; - memcpy(&value, bytes, len); - set_csr(addr / (max_xlen / 8), value); - return true; - } catch (trap_illegal_instruction& t) { - return false; + switch (addr) + { + case 0: + state.mip &= ~MIP_MSIP; + if (bytes[0] & 1) + state.mip |= MIP_MSIP; + return true; + + default: + return false; } } diff --git a/riscv/sim.cc b/riscv/sim.cc index a4ae309..db08cb2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -142,11 +142,13 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) void sim_t::make_config_string() { - reg_t boot_rom_addr = DEFAULT_RSTVEC; - reg_t boot_rom_size = 0x2000; - reg_t rtc_addr = boot_rom_addr + boot_rom_size; + reg_t rtc_addr = EXT_IO_BASE; bus.add_device(rtc_addr, rtc.get()); + const int align = 0x1000; + reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align; + reg_t cpu_size = align; + uint32_t reset_vec[8] = { 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector 0x00028067, // jump straight to DRAM_BASE @@ -154,7 +156,7 @@ void sim_t::make_config_string() 0, // config string pointer 0, 0, 0, 0 // trap vector }; - reset_vec[3] = boot_rom_addr + sizeof(reset_vec); // config string pointer + reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); @@ -180,16 +182,18 @@ void sim_t::make_config_string() " " << "0 {\n" << // hart 0 on core i " isa " << procs[i]->isa_string << ";\n" " timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n" + " ipi 0x" << cpu_addr << ";\n" " };\n" " };\n"; + bus.add_device(cpu_addr, procs[i]); + cpu_addr += cpu_size; } s << "};\n"; config_string = s.str(); rom.insert(rom.end(), config_string.begin(), config_string.end()); - assert(rom.size() < boot_rom_size); - rom.resize(boot_rom_size); + rom.resize((rom.size() / align + 1) * align); boot_rom.reset(new rom_device_t(rom)); - bus.add_device(boot_rom_addr, boot_rom.get()); + bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } |