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2010-10-15[sim] made softfloat files C instead of C++Andrew Waterman113-114/+129
2010-10-11[sim] added writeback tracingAndrew Waterman1-2/+26
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman1-27/+19
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman1-2/+2
2010-10-05[xcc] removed CEXC field from FSRAndrew Waterman1-15/+5
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman5-7/+13
now, the evec register holds the address that all traps vector to, and the cause register is set with the trap number.
2010-10-02[sim, xcc] changed cvt/trunc to use GPRs for int argsAndrew Waterman16-16/+24
this way, we don't have to futz with storing integers in recoded floating-point registers. too bad we lose some decoupling.
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman5-49/+49
this is symmetric with fp stores, so we only need one decoding pipe
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman2-108/+115
...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
2010-09-23[xcc, sim] eliminated zero-extended immediatesAndrew Waterman4-6/+5
This is a big commit because it involved rewriting gcc's algorithm for generating constants.
2010-09-22[sim] fixed bug in which shift operands were reversedAndrew Waterman6-6/+6
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman146-243/+251
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman5-11/+11
This will simplify control logic (since every branch has a logical inverse)
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman7-29/+29
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman14-87/+72
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman3-8/+8
2010-09-11[xcc] fixed broken 32-bit FP ABIAndrew Waterman1-0/+0
2010-09-10[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitAndrew Waterman4-5/+9
2010-09-10[sim, pk] cleaned up exception vectors and FP exc flagsAndrew Waterman3-15/+24
2010-09-10[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Yunsup Lee3-147/+148
2010-09-09[opcodes,sim,xcc] move opcodes for 3 source instructionsYunsup Lee1-56/+67
2010-09-09Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"Andrew Waterman5-4/+4
This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison.
2010-09-09Merge branch 'master' of /project/eecs/parlab/git/projects/riscvAndrew Waterman6-37/+60
Conflicts: sim/riscv/insns/mtpcr.h sim/riscv/processor.cc
2010-09-09[pk, sim] added interrupt support to sim; added timer interruptAndrew Waterman7-17/+52
2010-09-08[sim] add while to interactive_untilYunsup Lee6-38/+61
2010-09-08[sim] change applink for tohost/fromhost (forgot one file)Yunsup Lee1-0/+2
2010-09-08[sim] change applink for tohost/fromhostYunsup Lee2-2/+12
2010-09-07[xcc, sim] added slei/sleui in lieu of slti/sltiuAndrew Waterman5-4/+4
Rationale was that since we have the datapath for rc = (ra < rb), it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
2010-09-07[sim] yet another fix stdint.h __STDC_LIMIT_MACROS problemYunsup Lee1-1/+1
2010-09-07[sim] fix stdint.h __STDC_LIMIT_MACROS problemYunsup Lee1-1/+1
2010-09-07[sim, xcc] branches now have 2-byte-aligned displacementsAndrew Waterman2-2/+6
This will facilitate 16-bit instructions later on
2010-09-06[sim, xcc] added PCRs to replace k0 and k1Andrew Waterman7-47/+16
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman12-37/+61
2010-09-06[sim] fixed bug in msub.d; added ability to print FPRs in debug modeAndrew Waterman3-1/+40
2010-09-06[sim] added atomic memory operationsAndrew Waterman17-18/+184
2010-08-24[xcc] argc/argv work for 32b programsAndrew Waterman1-1/+0
Some patch-up code runs as soon as the 32b version of crt1 begins running that massages the pointers accordingly.
2010-08-24[sim] privileged mode support for 32-bit operationAndrew Waterman4-20/+26
2010-08-22[xcc,sim] added fused multiply-add and its cousinsAndrew Waterman9-0/+80
2010-08-22[xcc,sim] Eliminated slori instructionAndrew Waterman1-5/+0
the "li" macro in RISC-V assembly isn't as efficient anymore for 64b constants, and "la" doesn't work for 64b addresses with ".set noat". But it's worth it to remove an ugly instruction.
2010-08-18[pk,fesvr] improved proxykernel build systemAndrew Waterman2-0/+71
Now uses a modified MCPPBS. Add --host=riscv to configure path. Front-end server now just searches PATH for riscv-pk, so just install the pk to somewhere in your path.
2010-08-18[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2bAndrew Waterman178-9920/+461
2010-08-17[sim] specialized softfloat for riscvAndrew Waterman5-8/+7
2010-08-17[sim] added riscv folder to softfloatAndrew Waterman12-0/+442
2010-08-17[sim] added SoftFloat-3 sourceAndrew Waterman118-0/+9111
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman87-503/+537
The intersection of the Hauser FP and MIPS FP is implemented.
2010-08-09[sim] removed unused elf loaderAndrew Waterman5-89/+0
2010-08-09[sim] added softfloatAndrew Waterman6-0/+6661
2010-08-05[sim,xcc] Added first few Hauser FP insns (sign-injection)Andrew Waterman21-48/+69
Also updated FPmove test case to test negation and moving between FP regs
2010-08-04[sim] Bug fixes in shifts, plus a new test caseAndrew Waterman3-3/+3
2010-08-04[xcc] Removed ctc1, cfc1 instructions; added fp move test caseAndrew Waterman3-18/+0
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