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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-04 20:28:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-04 20:28:47 -0700 |
| commit | ae3bcd0a39ddd8538cd136dbae6ef14344405114 (patch) | |
| tree | 673078ea5b2cbbb1a9cc061d183ed04997a2eb63 | |
| parent | 7134cf8d9e4cabcaaa12839733468576402e2eb9 (diff) | |
| download | riscv-isa-sim-ae3bcd0a39ddd8538cd136dbae6ef14344405114.zip riscv-isa-sim-ae3bcd0a39ddd8538cd136dbae6ef14344405114.tar.gz riscv-isa-sim-ae3bcd0a39ddd8538cd136dbae6ef14344405114.tar.bz2 | |
[sim] Bug fixes in shifts, plus a new test case
| -rw-r--r-- | riscv/insns/srav.h | 2 | ||||
| -rw-r--r-- | riscv/insns/srlvw.h | 2 | ||||
| -rw-r--r-- | riscv/insns/srlw.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h index ec6fee8..e01fcd5 100644 --- a/riscv/insns/srav.h +++ b/riscv/insns/srav.h @@ -1,2 +1,2 @@ require64; -RC = RB >> (RA & 0x3F); +RC = sreg_t(RB) >> (RA & 0x3F); diff --git a/riscv/insns/srlvw.h b/riscv/insns/srlvw.h index 7e1755f..c523b59 100644 --- a/riscv/insns/srlvw.h +++ b/riscv/insns/srlvw.h @@ -1 +1 @@ -RC = sext32(RB >> (RA & 0x1F)); +RC = sext32((uint32_t)RB >> (RA & 0x1F)); diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h index 0537a1c..9e41c8c 100644 --- a/riscv/insns/srlw.h +++ b/riscv/insns/srlw.h @@ -1 +1 @@ -RC = sext32(RB >> SHAMT); +RC = sext32((uint32_t)RB >> SHAMT); |