index
:
riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speed2
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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Lines
2019-03-31
Add fesvr; only globally install fesvr headers/libs
static-link
Andrew Waterman
41
-232
/
+6512
2019-03-30
Don't install generated headers
Andrew Waterman
1
-1
/
+1
2019-03-30
Statically link the built-in libraries
Andrew Waterman
1
-11
/
+10
2019-03-30
RV32Q is not invalid
Andrew Waterman
1
-3
/
+0
2019-03-30
Make --help return 0 after printing the help message
Andrew Waterman
1
-4
/
+11
2019-03-27
Respect interrupt priorities even when not delegated
Andrew Waterman
1
-9
/
+13
2019-03-12
include sys/types.h for suseconds_t (#285)
nmeum
1
-0
/
+1
2019-03-04
Implement halt groups (#280)
Tim Newsome
3
-176
/
+649
2019-02-28
Further fix PMP checks for partially-matching accesses (#270)
Andrew Waterman
1
-3
/
+4
2019-02-19
Fix small bug in debug example. (#277)
Tim Newsome
1
-7
/
+9
2019-02-04
Fix use of old name `riscv-isa-run` (#269)
Luís Marques
1
-1
/
+1
2019-02-04
Merge pull request #274 from hakrdinesh/master
Andrew Waterman
3
-1
/
+22
2019-02-04
need to install dtc pkg on openbsd
Dinesh Thirumurthy
1
-2
/
+2
2019-02-04
doc typo fix on README.md, sorry.
Dinesh Thirumurthy
1
-1
/
+1
2019-02-04
build instructions for openbsd
Dinesh Thirumurthy
1
-0
/
+14
2019-02-04
fixing compilation errors on openbsd
Dinesh Thirumurthy
1
-0
/
+7
2019-02-04
bash can be at /usr/local/bin, on openbsd
Dinesh Thirumurthy
1
-1
/
+1
2019-01-28
Fix PMP checks for partially-matching accesses (#270)
Andrew Waterman
2
-8
/
+21
2019-01-09
Merge pull request #265 from riscv/debug_test
Tim Newsome
7
-38
/
+98
2018-12-21
Reserve the PMP R=0 W=1 combination
Andrew Waterman
1
-2
/
+5
2018-12-19
Flush I/O buffers before forking
Andrew Waterman
1
-0
/
+1
2018-12-13
Add --dmi-rti and --abstract-rti to test OpenOCD.
Tim Newsome
7
-38
/
+98
2018-12-03
Correct address autoincrement calls. (#263)
Tim Newsome
1
-2
/
+5
2018-11-09
commands render correctly in README.md now, included in code block
naufal
1
-1
/
+2
2018-11-06
Report misaligned-address exception on failed store-conditionals
Andrew Waterman
2
-14
/
+8
2018-10-19
Merge pull request #247 from heshamelmatary/noisy_until
Palmer Dabbelt
2
-6
/
+20
2018-10-18
Provide a noisy until interactive command
Hesham Almatary
2
-6
/
+20
2018-10-04
Set marchid to assigned value 5
Andrew Waterman
1
-1
/
+1
2018-10-03
fix disassembly of c.addi4spn
Andrew Waterman
1
-1
/
+1
2018-09-27
Add comment about CSR read side effects
Andrew Waterman
1
-0
/
+3
2018-09-25
For backwards compatibility, reset PMP to permit all accesses
Andrew Waterman
1
-0
/
+3
2018-09-25
Add PMP support
Andrew Waterman
4
-24
/
+147
2018-09-24
Add "--log-cache-miss" option to generate a log of cache miss. (#241)
takeoverjp
3
-2
/
+19
2018-09-12
Update README
Andrew Waterman
1
-9
/
+6
2018-09-06
Merge pull request #235 from riscv/sba
Tim Newsome
1
-1
/
+1
2018-09-05
Fix cut-and-paste bug in 64-bit SBA loads.
Tim Newsome
1
-1
/
+1
2018-08-24
Handle spike-dasm inputs with leading 0x correctly
Andrew Waterman
1
-9
/
+17
2018-08-23
Add dummy custom debug registers, to test OpenOCD. (#233)
Tim Newsome
2
-0
/
+18
2018-08-23
Fix several disassembler bugs
Andrew Waterman
2
-57
/
+89
2018-08-23
Add --disable-dtb option to suppress writing the DTB to memory
Andrew Waterman
3
-2
/
+11
2018-08-22
Make IRQ_COP read-only/undelegable unless coprocessor is present
Andrew Waterman
1
-1
/
+2
2018-08-21
Instantiate disassembler after max_xlen is known
Andrew Waterman
1
-1
/
+5
2018-08-17
Don't increment instret immediately after it is written (#231)
Andrew Waterman
1
-0
/
+6
2018-08-10
Fix 2 trigger corner cases. (#229)
Tim Newsome
2
-6
/
+14
2018-07-31
Make sstatus.MXR readable
Andrew Waterman
1
-1
/
+1
2018-07-23
Fix using the uninitialized disassemble object. (#220)
SeungRyeol Lee
1
-1
/
+1
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
9
-11
/
+34
2018-06-11
Merge pull request #212 from riscv/hartsel
Tim Newsome
3
-285
/
+303
2018-06-11
Update debug_defines.h
Tim Newsome
3
-285
/
+303
2018-05-31
Put simif_t declaration in its own file. (#209)
Andy Wright
7
-16
/
+27
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