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2021-04-16Merge pull request #694 from marcfedorow/p-extp-ext-0.5.2ChunPing Chung6-30/+24
2021-03-30Merge pull request #685 from marcfedorow/p-extChunPing Chung6-15/+15
2021-03-30Merge pull request #678 from marcfedorow/p-extChunPing Chung1-7/+7
2021-03-08rvp: update readme for p-ext 0.5.2Chun-Ping Chung1-1/+1
2021-03-08rvp: change ov csr to ucode to match v0.5.2 specChun-Ping Chung103-135/+143
2021-03-08rvp: disasm: add rv64 only instructions supportChun-Ping Chung1-2/+76
2021-03-08rvp: disasm: remove redundant tabChun-Ping Chung1-90/+90
2021-03-08rvp: add rv64 only non-simd 32-bit shift instructionsChun-Ping Chung2-0/+10
2021-03-08rvp: add rv64 only 32-bit parallel mul & add instructionsChun-Ping Chung15-13/+128
2021-03-08rvp: add rv64 only 32-bit mul & add instructionsChun-Ping Chung4-0/+24
2021-03-08rvp: add rv64 only 32-bit miscellaneous instructionsChun-Ping Chung6-0/+26
2021-03-08rvp: add rv64 only 32-bit multiply instructionsChun-Ping Chung3-0/+8
2021-03-08rvp: add rv64 only Q15 simd instructionsChun-Ping Chung10-0/+135
2021-03-08rvp: add 32 bits shift simd instructionsChun-Ping Chung15-0/+107
2021-03-08rvp: fix left shift saturation bugChun-Ping Chung13-68/+44
2021-03-08rvp: add 32 bits add/sub simd instructionsChun-Ping Chung32-2/+227
2021-03-08rvp: disasm: add non-simd instruction supportChun-Ping Chung1-0/+49
2021-03-08rvp: add Q31 saturation instructionsChun-Ping Chung21-5/+170
2021-03-08rvp: add non simd miscellaneous instructionsChun-Ping Chung12-0/+80
2021-03-08rvp: add rdov/clrov and fix khm16 behavior of setting OV flagChun-Ping Chung3-7/+10
2021-03-08rvp: add 32-bit computation instructionsChun-Ping Chung10-0/+45
2021-03-08rvp: fix kmar64/kmsr64 saturation behaviorChun-Ping Chung2-10/+50
2021-03-08rvp: add Q15 saturation instructionsChun-Ping Chung9-11/+79
2021-03-08rvp: disasm: add 64 bit profile instruction supportChun-Ping Chung1-0/+30
2021-03-08rvp: add 16-bit mul with 64-bit add/sub instructionsChun-Ping Chung11-0/+51
2021-03-08rvp: add 32-bit mul with 64-bit add/sub instructionsChun-Ping Chung10-0/+60
2021-03-08rvp: add 64-bit add & sub instructionsChun-Ping Chung12-0/+122
2021-03-08rvp: add signed 16 x 64 add/subtract InstructionsChun-Ping Chung2-0/+11
2021-03-08rvp: add partial simd miscellaneous instructionsChun-Ping Chung10-3/+83
2021-03-08rvp: refactor some p-ext macro codeChun-Ping Chung3-98/+106
2021-03-08rvp: use stdint to replace hardcode max/minimumChun-Ping Chung20-53/+55
2021-03-08rvp: add signed 16x32 add/subtract instructionsChun-Ping Chung21-1/+131
2021-03-08rvp: change reduction marcro definitionChun-Ping Chung4-20/+42
2021-03-08rvp: fix some styleChun-Ping Chung12-116/+44
2021-03-08rvp: add msw 32x16 multiply & add instructionsChun-Ping Chung18-0/+209
2021-03-08rvp: change to use extract64Chun-Ping Chung1-5/+2
2021-03-08rvp: add msw 32x32 multiply & add instructionsChun-Ping Chung10-0/+90
2021-03-08rvp: fix missing initial value of pdChun-Ping Chung1-17/+17
2021-03-08rvp: add kadd32, [su]maqa[_su] instructionsChun-Ping Chung7-0/+71
2021-03-08rvp: add pk[bb,bt,tt,tb][16,32] instructionsChun-Ping Chung11-0/+47
2021-03-08rvp: rename some macro argumentChun-Ping Chung1-85/+79
2021-03-08rvp: update encoding.h generated from riscv-opcode p-ext branchChun-Ping Chung1-122/+745
2021-03-08rvp: fix rvp support versionChun-Ping Chung1-1/+1
2021-03-08rvp: update readme for p-ext simd instructionsChun-Ping Chung1-0/+1
2021-03-08rvp: disasm: add simd instruction supportChun-Ping Chung1-0/+136
2021-03-08rvp: update encoding.h and riscv.mk.inChun-Ping Chung2-0/+494
2021-03-08rvp: update suppported extention and add restrictionChun-Ping Chung2-1/+8
2021-03-08rvp: add 8 bits unpacking simd instructionsChun-Ping Chung11-0/+40
2021-03-08rvp: add 8/16 bits misc simd instructionsChun-Ping Chung23-1/+200
2021-03-08rvp: add 8/16 bits multiply simd instructionsChun-Ping Chung13-1/+144
generated by cgit v1.1 at 2024-10-19 22:13:02 +0000