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8 daysMerge pull request #1829 from NXP/update-zilsd-to-v0.10HEADmasterAndrew Waterman9-15/+15
8 daysUpdated load/store pair for RV32 to v0.10Christian Herber9-15/+15
10 daysMerge pull request #1822 from howjmay/typosAndrew Waterman5-6/+6
10 daysfix typosYang Hau5-6/+6
11 daysMerge pull request #1823 from YenHaoChen/pr-haltAndrew Waterman1-3/+2
11 daysMerge pull request #1826 from riscv-software-src/fix-1825Andrew Waterman1-7/+39
12 daysChange -H flag into --haltedYenHaoChen1-3/+2
12 daysFix f64_to_bf16 raising underflow when it shouldn'tAndrew Waterman1-7/+39
2024-09-27Merge pull request #1819 from riscv-software-src/ss-cbo-faultAndrew Waterman2-5/+6
2024-09-26Merge pull request #1820 from YenHaoChen/pr-haltAndrew Waterman4-6/+2
2024-09-27refactor: Merge halt and halt_on_reset variables in processor_tYenHaoChen3-5/+2
2024-09-27refactor: Move halt out of dcsrYenHaoChen5-5/+4
2024-09-26Raise store/AMO access fault on CBO to shadow-stack pageAndrew Waterman2-5/+6
2024-09-26Merge pull request #1816 from YenHaoChen/pr-haltAndrew Waterman1-0/+1
2024-09-26Only enter debug mode once with -H flag (halt_on_reset)YenHaoChen1-0/+1
2024-09-20Merge pull request #1812 from riscv-software-src/fix-1810Andrew Waterman1-2/+22
2024-09-20Validate Zvl ISA string correctlyAndrew Waterman1-2/+22
2024-09-20Merge pull request #1811 from riscv-software-src/fix-1810Andrew Waterman1-1/+1
2024-09-20Validate Zvl ISA string correctlyAndrew Waterman1-1/+1
2024-09-18Merge pull request #1804 from ved-rivos/ssdbltrp_typoAndrew Waterman1-1/+1
2024-09-17fix error in reading right sstatusVed Shanbhogue1-1/+1
2024-09-14Merge pull request #1807 from riscv-software-src/remove-compile-flagsJerry Zhao7-53/+5
2024-09-14Remove leftover config.h includes in dasm/log-parserJerry Zhao2-2/+0
2024-09-14Remove --with-priv compile flagJerry Zhao5-25/+2
2024-09-14Remove --with-isa compile-time optionJerry Zhao6-26/+3
2024-09-11Merge pull request #1796 from cyyself/tmp_mcountinhibitAndrew Waterman4-4/+19
2024-09-11Merge pull request #1793 from rtwfroody/native_triggers2YenHaoChen5-26/+53
2024-09-09Only implement one solution for native triggers.Tim Newsome2-15/+29
2024-09-09triggers: Move allow_action() into common_match()Tim Newsome2-23/+28
2024-09-05Make allow_action() take proc instead of stateTim Newsome2-6/+7
2024-09-05Work if tcontrol doesn't exist.Tim Newsome3-3/+10
2024-09-06add support for mcountinhibit CSRYangyu Chen4-4/+19
2024-09-02Merge pull request #1797 from YenHaoChen/pr-vectorAndrew Waterman1-20/+48
2024-09-03vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector wideni...YenHaoChen1-4/+4
2024-09-03vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single...YenHaoChen1-8/+18
2024-09-03vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector wideni...YenHaoChen1-4/+6
2024-09-03vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single...YenHaoChen1-4/+20
2024-09-02Merge pull request #1788 from riscv-software-src/support-larger-addressesAndrew Waterman4-43/+36
2024-08-30Merge pull request #1779 from rtwfroody/trigger_timingAndrew Waterman1-1/+8
2024-08-29Merge pull request #1791 from YenHaoChen/pr-pmAndrew Waterman1-1/+1
2024-08-29pointer masking: Always apply sstatus.MXR regardless of effective VYenHaoChen1-1/+1
2024-08-28Merge pull request #1789 from YenHaoChen/pr-pmAndrew Waterman1-1/+1
2024-08-28pointer masking: Consider effective v bit instead of current v bitYenHaoChen1-1/+1
2024-08-27Merge pull request #1787 from riscv-software-src/fix-cfg-privJerry Zhao1-1/+1
2024-08-27Lift restriction on physical-address sizeAndrew Waterman3-18/+4
2024-08-27Use create_mem_region for legacy -m argumentAndrew Waterman1-3/+3
2024-08-27Check size_t bounds overflow in create_mem_regionAndrew Waterman1-2/+4
2024-08-27Factor out create_mem_region from parse_mem_layoutAndrew Waterman1-36/+41
2024-08-27Merge pull request #1786 from YenHaoChen/pr-mcontrolAndrew Waterman2-6/+8
2024-08-27Use cmdline --priv flag when parsing proc configurations from DTBJerry Zhao1-1/+1
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