aboutsummaryrefslogtreecommitdiff
path: root/riscv
diff options
context:
space:
mode:
Diffstat (limited to 'riscv')
-rw-r--r--riscv/csrs.cc29
-rw-r--r--riscv/csrs.h12
-rw-r--r--riscv/decode_macros.h20
-rw-r--r--riscv/encoding.h8
-rw-r--r--riscv/execute.cc2
-rw-r--r--riscv/insns/c_jalr.h4
-rw-r--r--riscv/insns/c_jr.h4
-rw-r--r--riscv/insns/c_lui.h2
-rw-r--r--riscv/insns/dret.h3
-rw-r--r--riscv/insns/jalr.h4
-rw-r--r--riscv/insns/lpad.h6
-rw-r--r--riscv/insns/mret.h4
-rw-r--r--riscv/insns/sret.h6
-rw-r--r--riscv/insns/vcompress_vm.h2
-rw-r--r--riscv/insns/wfi.h8
-rw-r--r--riscv/interactive.cc4
-rw-r--r--riscv/isa_parser.h1
-rw-r--r--riscv/mmu.cc2
-rw-r--r--riscv/mmu.h42
-rw-r--r--riscv/ns16550.cc7
-rw-r--r--riscv/overlap_list.h1
-rw-r--r--riscv/processor.cc105
-rw-r--r--riscv/processor.h13
-rw-r--r--riscv/riscv.mk.in6
-rw-r--r--riscv/trap.h1
-rw-r--r--riscv/v_ext_macros.h5
26 files changed, 224 insertions, 77 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index 0e8bf6d..4a612e5 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -285,7 +285,8 @@ mseccfg_csr_t::mseccfg_csr_t(processor_t* const proc, const reg_t addr):
void mseccfg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
- if (!proc->extension_enabled(EXT_SMEPMP))
+ if (!proc->extension_enabled(EXT_SMEPMP) &&
+ !proc->extension_enabled(EXT_ZICFILP))
throw trap_illegal_instruction(insn.bits());
}
@@ -322,6 +323,11 @@ bool mseccfg_csr_t::unlogged_write(const reg_t val) noexcept {
proc->get_mmu()->flush_tlb();
+ if (proc->extension_enabled(EXT_ZICFILP)) {
+ new_val &= ~MSECCFG_MLPE;
+ new_val |= (val & MSECCFG_MLPE);
+ }
+
return basic_csr_t::unlogged_write(new_val);
}
@@ -414,6 +420,7 @@ reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept {
| (has_fs ? SSTATUS_FS : 0)
| (proc->any_custom_extensions() ? SSTATUS_XS : 0)
| (has_vs ? SSTATUS_VS : 0)
+ | (proc->extension_enabled(EXT_ZICFILP) ? SSTATUS_SPELP : 0)
;
}
@@ -497,7 +504,9 @@ bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept {
| (proc->extension_enabled('S') ? MSTATUS_TSR : 0)
| (has_page ? MSTATUS_TVM : 0)
| (has_gva ? MSTATUS_GVA : 0)
- | (has_mpv ? MSTATUS_MPV : 0);
+ | (has_mpv ? MSTATUS_MPV : 0)
+ | (proc->extension_enabled(EXT_ZICFILP) ? (MSTATUS_SPELP | MSTATUS_MPELP) : 0)
+ ;
const reg_t requested_mpp = proc->legalize_privilege(get_field(val, MSTATUS_MPP));
const reg_t adjusted_val = set_field(val, MSTATUS_MPP, requested_mpp);
@@ -897,6 +906,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
| (1 << CAUSE_LOAD_PAGE_FAULT)
| (1 << CAUSE_STORE_PAGE_FAULT)
| (proc->extension_enabled('H') ? hypervisor_exceptions : 0)
+ | (1 << CAUSE_SOFTWARE_CHECK_FAULT)
;
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
@@ -1284,7 +1294,8 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr):
ebreakvu(false),
halt(false),
v(false),
- cause(0) {
+ cause(0),
+ pelp(elp_t::NO_LP_EXPECTED) {
}
void dcsr_csr_t::verify_permissions(insn_t insn, bool write) const {
@@ -1307,6 +1318,7 @@ reg_t dcsr_csr_t::read() const noexcept {
result = set_field(result, DCSR_STEP, step);
result = set_field(result, DCSR_PRV, prv);
result = set_field(result, CSR_DCSR_V, v);
+ result = set_field(result, DCSR_PELP, pelp);
return result;
}
@@ -1321,13 +1333,17 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept {
ebreakvu = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVU) : false;
halt = get_field(val, DCSR_HALT);
v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false;
+ pelp = proc->extension_enabled(EXT_ZICFILP) ?
+ static_cast<elp_t>(get_field(val, DCSR_PELP)) : elp_t::NO_LP_EXPECTED;
return true;
}
-void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv, bool v) noexcept {
+void dcsr_csr_t::update_fields(const uint8_t cause, const reg_t prv,
+ const bool v, const elp_t pelp) noexcept {
this->cause = cause;
this->prv = prv;
this->v = v;
+ this->pelp = pelp;
log_write();
}
@@ -1533,6 +1549,11 @@ void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
masked_csr_t::verify_permissions(insn, write);
}
+bool henvcfg_csr_t::unlogged_write(const reg_t val) noexcept {
+ const reg_t mask = menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_ADUE);
+ return envcfg_csr_t::unlogged_write((masked_csr_t::read() & ~mask) | (val & mask));
+}
+
stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask):
basic_csr_t(proc, addr, 0), intr_mask(imask) {
}
diff --git a/riscv/csrs.h b/riscv/csrs.h
index b3dfe1c..2595243 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -21,6 +21,11 @@
class processor_t;
struct state_t;
+enum struct elp_t {
+ NO_LP_EXPECTED = 0,
+ LP_EXPECTED = 1,
+};
+
// Parent, abstract class for all CSRs
class csr_t {
public:
@@ -485,6 +490,9 @@ class henvcfg_csr_t final: public envcfg_csr_t {
virtual void verify_permissions(insn_t insn, bool write) const override;
+ protected:
+ virtual bool unlogged_write(const reg_t val) noexcept override;
+
private:
csr_t_p menvcfg;
};
@@ -676,7 +684,8 @@ class dcsr_csr_t: public csr_t {
dcsr_csr_t(processor_t* const proc, const reg_t addr);
virtual void verify_permissions(insn_t insn, bool write) const override;
virtual reg_t read() const noexcept override;
- void write_cause_and_prv(uint8_t cause, reg_t prv, bool v) noexcept;
+ void update_fields(const uint8_t cause, const reg_t prv,
+ const bool v, const elp_t pelp) noexcept;
protected:
virtual bool unlogged_write(const reg_t val) noexcept override;
public:
@@ -690,6 +699,7 @@ class dcsr_csr_t: public csr_t {
bool halt;
bool v;
uint8_t cause;
+ elp_t pelp;
};
typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p;
diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
index e31da5c..4050000 100644
--- a/riscv/decode_macros.h
+++ b/riscv/decode_macros.h
@@ -321,3 +321,23 @@ inline long double to_f(float128_t f) { long double r; memcpy(&r, &f, sizeof(r))
reg_t h##field = get_field(STATE.henvcfg->read(), HENVCFG_##field)
#endif
+
+#define software_check(x, tval) (unlikely(!(x)) ? throw trap_software_check(tval) : (void) 0)
+#define ZICFILP_xLPE(v, prv) \
+ ({ \
+ reg_t lpe = 0ULL; \
+ if (p->extension_enabled(EXT_ZICFILP)) { \
+ DECLARE_XENVCFG_VARS(LPE); \
+ const reg_t msecLPE = get_field(STATE.mseccfg->read(), MSECCFG_MLPE); \
+ switch (prv) { \
+ case PRV_U: lpe = p->extension_enabled('S') ? sLPE : mLPE; break; \
+ case PRV_S: lpe = (v) ? hLPE : mLPE; break; \
+ case PRV_M: lpe = msecLPE; break; \
+ default: abort(); \
+ } \
+ } \
+ lpe; \
+ })
+#define ZICFILP_IS_LP_EXPECTED(reg_num) \
+ (((reg_num) != 1 && (reg_num) != 5 && (reg_num) != 7) ? \
+ elp_t::LP_EXPECTED : elp_t::NO_LP_EXPECTED)
diff --git a/riscv/encoding.h b/riscv/encoding.h
index 249b3fa..ff3f743 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -4,7 +4,7 @@
/*
* This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (a014979)
+ * https://github.com/riscv/riscv-opcodes (4ad822d)
*/
#ifndef RISCV_CSR_ENCODING_H
@@ -346,6 +346,9 @@
#define SRMCFG_RCID 0x00000FFF
#define SRMCFG_MCID 0x0FFF0000
+/* software check exception xtval codes */
+#define LANDING_PAD_FAULT 2
+
#ifdef __riscv
#if __riscv_xlen == 64
@@ -1464,6 +1467,8 @@
#define MASK_LH_AQ 0xfdf0707f
#define MATCH_LHU 0x5003
#define MASK_LHU 0x707f
+#define MATCH_LPAD 0x17
+#define MASK_LPAD 0xfff
#define MATCH_LQ 0x300f
#define MASK_LQ 0x707f
#define MATCH_LR_D 0x1000302f
@@ -4245,6 +4250,7 @@ DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU)
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
DECLARE_INSN(lh_aq, MATCH_LH_AQ, MASK_LH_AQ)
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD)
DECLARE_INSN(lq, MATCH_LQ, MASK_LQ)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 4f5860b..b2532c9 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -280,6 +280,7 @@ void processor_t::step(size_t n)
in_wfi = false;
insn_fetch_t fetch = mmu->load_insn(pc);
+ execute_insn_prehook(fetch.insn);
if (debug && !state.serialized)
disasm(fetch.insn);
pc = execute_insn_logged(this, pc, fetch);
@@ -291,6 +292,7 @@ void processor_t::step(size_t n)
// Main simulation loop, fast path.
for (auto ic_entry = _mmu->access_icache(pc); ; ) {
auto fetch = ic_entry->data;
+ execute_insn_prehook(fetch.insn);
pc = execute_insn_fast(this, pc, fetch);
ic_entry = ic_entry->next;
if (unlikely(ic_entry->tag != pc))
diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h
index 0a00f1c..12bc7f9 100644
--- a/riscv/insns/c_jalr.h
+++ b/riscv/insns/c_jalr.h
@@ -3,3 +3,7 @@ require(insn.rvc_rs1() != 0);
reg_t tmp = npc;
set_pc(RVC_RS1 & ~reg_t(1));
WRITE_REG(X_RA, tmp);
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+ STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1());
+}
diff --git a/riscv/insns/c_jr.h b/riscv/insns/c_jr.h
index 020cafd..c5162e9 100644
--- a/riscv/insns/c_jr.h
+++ b/riscv/insns/c_jr.h
@@ -1,3 +1,7 @@
require_extension(EXT_ZCA);
require(insn.rvc_rs1() != 0);
set_pc(RVC_RS1 & ~reg_t(1));
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+ STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1());
+}
diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index 3e0e02f..7a82c13 100644
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -4,7 +4,7 @@ if (insn.rvc_rd() == 2) { // c.addi16sp
WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
} else if (insn.rvc_imm() != 0) { // c.lui
WRITE_RD(insn.rvc_imm() << 12);
-} else if ((insn.rvc_rd() & 1) != 0) { // c.mop.N
+} else if ((insn.rvc_rd() & 0x11) == 1) { // c.mop.N
#include "c_mop_N.h"
} else {
require(false);
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h
index 2abcc7d..bdcf3db 100644
--- a/riscv/insns/dret.h
+++ b/riscv/insns/dret.h
@@ -1,5 +1,8 @@
require(STATE.debug_mode);
set_pc_and_serialize(STATE.dpc->read());
+if (ZICFILP_xLPE(STATE.dcsr->v, STATE.dcsr->prv)) {
+ STATE.elp = STATE.dcsr->pelp;
+}
p->set_privilege(STATE.dcsr->prv, STATE.dcsr->v);
if (STATE.prv < PRV_M)
STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_MPRV);
diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index 386e8db..0622a22 100644
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,7 @@
reg_t tmp = npc;
set_pc((RS1 + insn.i_imm()) & ~reg_t(1));
WRITE_RD(tmp);
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+ STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rs1());
+}
diff --git a/riscv/insns/lpad.h b/riscv/insns/lpad.h
new file mode 100644
index 0000000..733e91d
--- /dev/null
+++ b/riscv/insns/lpad.h
@@ -0,0 +1,6 @@
+if (ZICFILP_xLPE(STATE.v, STATE.prv) && STATE.elp == elp_t::LP_EXPECTED) {
+ software_check(pc % 4 == 0 &&
+ ((READ_REG(7) & 0xFFFFF000ULL) == (static_cast<uint64_t>(insn.u_imm()) & 0xFFFFF000ULL) || insn.u_imm() == 0LL),
+ LANDING_PAD_FAULT);
+ STATE.elp = elp_t::NO_LP_EXPECTED;
+}
diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h
index 7cb1f62..1133e86 100644
--- a/riscv/insns/mret.h
+++ b/riscv/insns/mret.h
@@ -9,6 +9,10 @@ s = set_field(s, MSTATUS_MIE, get_field(s, MSTATUS_MPIE));
s = set_field(s, MSTATUS_MPIE, 1);
s = set_field(s, MSTATUS_MPP, p->extension_enabled('U') ? PRV_U : PRV_M);
s = set_field(s, MSTATUS_MPV, 0);
+if (ZICFILP_xLPE(prev_virt, prev_prv)) {
+ STATE.elp = static_cast<elp_t>(get_field(s, MSTATUS_MPELP));
+ s = set_field(s, MSTATUS_MPELP, elp_t::NO_LP_EXPECTED);
+}
STATE.mstatus->write(s);
if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change
p->set_privilege(prev_prv, prev_virt);
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
index 4c7305d..aeaf087 100644
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@@ -13,7 +13,6 @@ reg_t prev_prv = get_field(s, MSTATUS_SPP);
s = set_field(s, MSTATUS_SIE, get_field(s, MSTATUS_SPIE));
s = set_field(s, MSTATUS_SPIE, 1);
s = set_field(s, MSTATUS_SPP, PRV_U);
-STATE.sstatus->write(s);
bool prev_virt = STATE.v;
if (!STATE.v) {
if (p->extension_enabled('H')) {
@@ -24,4 +23,9 @@ if (!STATE.v) {
STATE.mstatus->write(set_field(STATE.mstatus->read(), MSTATUS_MPRV, 0));
}
+if (ZICFILP_xLPE(prev_virt, prev_prv)) {
+ STATE.elp = static_cast<elp_t>(get_field(s, SSTATUS_SPELP));
+ s = set_field(s, SSTATUS_SPELP, elp_t::NO_LP_EXPECTED);
+}
+STATE.sstatus->write(s);
p->set_privilege(prev_prv, prev_virt);
diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index 7195345..d35b8ba 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -30,4 +30,4 @@ VI_GENERAL_LOOP_BASE
++pos;
}
-VI_LOOP_END;
+VI_LOOP_END_BASE;
diff --git a/riscv/insns/wfi.h b/riscv/insns/wfi.h
index 3411da0..5382072 100644
--- a/riscv/insns/wfi.h
+++ b/riscv/insns/wfi.h
@@ -1,9 +1,7 @@
-if (STATE.v && STATE.prv == PRV_U) {
- require_novirt();
-} else if (get_field(STATE.mstatus->read(), MSTATUS_TW)) {
+if (get_field(STATE.mstatus->read(), MSTATUS_TW)) {
require_privilege(PRV_M);
-} else if (STATE.v) { // VS-mode
- if (get_field(STATE.hstatus->read(), HSTATUS_VTW))
+} else if (STATE.v) {
+ if (STATE.prv == PRV_U || get_field(STATE.hstatus->read(), HSTATUS_VTW))
require_novirt();
} else if (p->extension_enabled('S')) {
// When S-mode is implemented, then executing WFI in
diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 8dc4828..71e26e6 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -413,7 +413,7 @@ void sim_t::interactive_run(const std::string& cmd, const std::vector<std::strin
step(1);
if (actual_steps < steps) {
- next_interactive_action = [=](){ interactive_run(cmd, {std::to_string(steps - actual_steps)}, noisy); };
+ next_interactive_action = [=, this](){ interactive_run(cmd, {std::to_string(steps - actual_steps)}, noisy); };
return;
}
@@ -768,7 +768,7 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str
step(1);
}
- next_interactive_action = [=](){ interactive_until(cmd, args, noisy); };
+ next_interactive_action = [=, this](){ interactive_until(cmd, args, noisy); };
}
void sim_t::interactive_dumpmems(const std::string& cmd, const std::vector<std::string>& args)
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index f310b97..f02b55d 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -87,6 +87,7 @@ typedef enum {
EXT_ZCMOP,
EXT_ZALASR,
EXT_SSQOSID,
+ EXT_ZICFILP,
NUM_ISA_EXTENSIONS
} isa_extension_t;
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 165be53..1a0c830 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -70,7 +70,7 @@ reg_t mmu_t::translate(mem_access_info_t access_info, reg_t len)
tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr)
{
- auto access_info = generate_access_info(vaddr, FETCH, {false, false, false});
+ auto access_info = generate_access_info(vaddr, FETCH, {});
check_triggers(triggers::OPERATION_EXECUTE, vaddr, access_info.effective_virt);
tlb_entry_t result;
diff --git a/riscv/mmu.h b/riscv/mmu.h
index a163fe4..4404e4c 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -39,9 +39,9 @@ struct tlb_entry_t {
};
struct xlate_flags_t {
- const bool forced_virt : 1;
- const bool hlvx : 1;
- const bool lr : 1;
+ const bool forced_virt : 1 {false};
+ const bool hlvx : 1 {false};
+ const bool lr : 1 {false};
bool is_special_access() const {
return forced_virt || hlvx || lr;
@@ -72,7 +72,7 @@ private:
mem_access_info_t generate_access_info(reg_t addr, access_type type, xlate_flags_t xlate_flags) {
if (!proc)
- return {addr, 0, false, {false, false, false}, type};
+ return {addr, 0, false, {}, type};
bool virt = proc->state.v;
reg_t mode = proc->state.prv;
if (type != FETCH) {
@@ -94,7 +94,7 @@ public:
~mmu_t();
template<typename T>
- T ALWAYS_INLINE load(reg_t addr, xlate_flags_t xlate_flags = {false, false, false}) {
+ T ALWAYS_INLINE load(reg_t addr, xlate_flags_t xlate_flags = {}) {
target_endian<T> res;
reg_t vpn = addr >> PGSHIFT;
bool aligned = (addr & (sizeof(T) - 1)) == 0;
@@ -114,30 +114,21 @@ public:
template<typename T>
T load_reserved(reg_t addr) {
- bool forced_virt = false;
- bool hlvx = false;
- bool lr = true;
- return load<T>(addr, {forced_virt, hlvx, lr});
+ return load<T>(addr, {.lr = true});
}
template<typename T>
T guest_load(reg_t addr) {
- bool forced_virt = true;
- bool hlvx = false;
- bool lr = false;
- return load<T>(addr, {forced_virt, hlvx, lr});
+ return load<T>(addr, {.forced_virt = true});
}
template<typename T>
T guest_load_x(reg_t addr) {
- bool forced_virt = true;
- bool hlvx = true;
- bool lr = false;
- return load<T>(addr, {forced_virt, hlvx, lr});
+ return load<T>(addr, {.forced_virt=true, .hlvx=true});
}
template<typename T>
- void ALWAYS_INLINE store(reg_t addr, T val, xlate_flags_t xlate_flags = {false, false, false}) {
+ void ALWAYS_INLINE store(reg_t addr, T val, xlate_flags_t xlate_flags = {}) {
reg_t vpn = addr >> PGSHIFT;
bool aligned = (addr & (sizeof(T) - 1)) == 0;
bool tlb_hit = tlb_store_tag[vpn % TLB_ENTRIES] == vpn;
@@ -155,10 +146,7 @@ public:
template<typename T>
void guest_store(reg_t addr, T val) {
- bool forced_virt = true;
- bool hlvx = false;
- bool lr = false;
- store(addr, val, {forced_virt, hlvx, lr});
+ store(addr, val, {.forced_virt=true});
}
// AMO/Zicbom faults should be reported as store faults
@@ -180,7 +168,7 @@ public:
template<typename T, typename op>
T amo(reg_t addr, op f) {
convert_load_traps_to_store_traps({
- store_slow_path(addr, sizeof(T), nullptr, {false, false, false}, false, true);
+ store_slow_path(addr, sizeof(T), nullptr, {}, false, true);
auto lhs = load<T>(addr);
store<T>(addr, f(lhs));
return lhs;
@@ -190,7 +178,7 @@ public:
template<typename T>
T amo_compare_and_swap(reg_t addr, T comp, T swap) {
convert_load_traps_to_store_traps({
- store_slow_path(addr, sizeof(T), nullptr, {false, false, false}, false, true);
+ store_slow_path(addr, sizeof(T), nullptr, {}, false, true);
auto lhs = load<T>(addr);
if (lhs == comp)
store<T>(addr, swap);
@@ -230,7 +218,7 @@ public:
for (size_t offset = 0; offset < blocksz; offset += 1)
check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt);
convert_load_traps_to_store_traps({
- const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), 1);
+ const reg_t paddr = translate(generate_access_info(addr, LOAD, {}), 1);
if (sim->reservable(paddr)) {
if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
tracer.clean_invalidate(paddr, blocksz, clean, inval);
@@ -249,10 +237,10 @@ public:
{
if (vaddr & (size-1)) {
// Raise either access fault or misaligned exception
- store_slow_path(vaddr, size, nullptr, {false, false, false}, false, true);
+ store_slow_path(vaddr, size, nullptr, {}, false, true);
}
- reg_t paddr = translate(generate_access_info(vaddr, STORE, {false, false, false}), 1);
+ reg_t paddr = translate(generate_access_info(vaddr, STORE, {}), 1);
if (sim->reservable(paddr))
return load_reservation_address == paddr;
else
diff --git a/riscv/ns16550.cc b/riscv/ns16550.cc
index a74aa74..e0b3251 100644
--- a/riscv/ns16550.cc
+++ b/riscv/ns16550.cc
@@ -2,6 +2,7 @@
#include <sstream>
#include "devices.h"
#include "processor.h"
+#include "mmu.h"
#include "term.h"
#include "sim.h"
#include "dts.h"
@@ -170,6 +171,9 @@ bool ns16550_t::load(reg_t addr, size_t len, uint8_t* bytes)
if (reg_io_width != len) {
return false;
}
+ if (addr + len > PGSIZE) {
+ return false;
+ }
addr >>= reg_shift;
addr &= 7;
@@ -230,6 +234,9 @@ bool ns16550_t::store(reg_t addr, size_t len, const uint8_t* bytes)
if (reg_io_width != len) {
return false;
}
+ if (addr + len > PGSIZE) {
+ return false;
+ }
addr >>= reg_shift;
addr &= 7;
val = bytes[0];
diff --git a/riscv/overlap_list.h b/riscv/overlap_list.h
index 2214be4..3084c36 100644
--- a/riscv/overlap_list.h
+++ b/riscv/overlap_list.h
@@ -21,3 +21,4 @@ DECLARE_OVERLAP_INSN(rstsa16, EXT_ZPN)
DECLARE_OVERLAP_INSN(rstsa32, EXT_ZPN)
DECLARE_OVERLAP_INSN(srli32_u, EXT_ZPN)
DECLARE_OVERLAP_INSN(umax32, EXT_ZPN)
+DECLARE_OVERLAP_INSN(lpad, EXT_ZICFILP)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index cfce08f..3a1eadb 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -94,6 +94,14 @@ processor_t::~processor_t()
delete disassembler;
}
+static void zicfilp_check_if_lpad_required(const elp_t elp, insn_t insn)
+{
+ if (unlikely(elp == elp_t::LP_EXPECTED)) {
+ // also see riscv/lpad.h for more checks performed
+ software_check((insn.bits() & MASK_LPAD) == MATCH_LPAD, LANDING_PAD_FAULT);
+ }
+}
+
static void bad_option_string(const char *option, const char *value,
const char *msg)
{
@@ -374,7 +382,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
(1 << CAUSE_USER_ECALL) |
(1 << CAUSE_FETCH_PAGE_FAULT) |
(1 << CAUSE_LOAD_PAGE_FAULT) |
- (1 << CAUSE_STORE_PAGE_FAULT);
+ (1 << CAUSE_STORE_PAGE_FAULT) |
+ (1 << CAUSE_SOFTWARE_CHECK_FAULT);
csrmap[CSR_HEDELEG] = hedeleg = std::make_shared<masked_csr_t>(proc, CSR_HEDELEG, hedeleg_mask, 0);
csrmap[CSR_HCOUNTEREN] = hcounteren = std::make_shared<masked_csr_t>(proc, CSR_HCOUNTEREN, counteren_mask, 0);
htimedelta = std::make_shared<basic_csr_t>(proc, CSR_HTIMEDELTA, 0);
@@ -408,7 +417,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
csrmap[CSR_TDATA3] = std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0);
csrmap[CSR_TINFO] = std::make_shared<const_csr_t>(proc, CSR_TINFO, 0);
}
- unsigned scontext_length = (xlen == 32 ? 16 : 34); // debug spec suggests 16-bit for RV32 and 34-bit for RV64
+ unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64
csrmap[CSR_SCONTEXT] = scontext = std::make_shared<masked_csr_t>(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0);
unsigned hcontext_length = (xlen == 32 ? 6 : 13) + (proc->extension_enabled('H') ? 1 : 0); // debug spec suggest 7-bit (6-bit) for RV32 and 14-bit (13-bit) for RV64 with (without) H extension
csrmap[CSR_HCONTEXT] = std::make_shared<masked_csr_t>(proc, CSR_HCONTEXT, (reg_t(1) << hcontext_length) - 1, 0);
@@ -443,7 +452,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
(proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
(proc->extension_enabled(EXT_SVADU) ? MENVCFG_ADUE: 0) |
(proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) |
- (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0);
+ (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0) |
+ (proc->extension_enabled(EXT_ZICFILP) ? MENVCFG_LPE : 0);
const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
menvcfg = std::make_shared<envcfg_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
if (xlen == 32) {
@@ -453,13 +463,15 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
csrmap[CSR_MENVCFG] = menvcfg;
}
const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
- (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
+ (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0) |
+ (proc->extension_enabled(EXT_ZICFILP) ? SENVCFG_LPE : 0);
csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
(proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
(proc->extension_enabled(EXT_SVADU) ? HENVCFG_ADUE: 0) |
(proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) |
- (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0);
+ (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0) |
+ (proc->extension_enabled(EXT_ZICFILP) ? HENVCFG_LPE : 0);
const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
if (xlen == 32) {
@@ -590,6 +602,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
last_inst_priv = 0;
last_inst_xlen = 0;
last_inst_flen = 0;
+
+ elp = elp_t::NO_LP_EXPECTED;
}
void processor_t::set_debug(bool value)
@@ -810,8 +824,10 @@ const char* processor_t::get_privilege_string()
void processor_t::enter_debug_mode(uint8_t cause)
{
+ const bool has_zicfilp = extension_enabled(EXT_ZICFILP);
state.debug_mode = true;
- state.dcsr->write_cause_and_prv(cause, state.prv, state.v);
+ state.dcsr->update_fields(cause, state.prv, state.v, state.elp);
+ state.elp = elp_t::NO_LP_EXPECTED;
set_privilege(PRV_M, false);
state.dpc->write(state.pc);
state.pc = DEBUG_ROM_ENTRY;
@@ -880,6 +896,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, state.prv);
s = set_field(s, MSTATUS_SIE, 0);
+ s = set_field(s, MSTATUS_SPELP, state.elp);
+ state.elp = elp_t::NO_LP_EXPECTED;
state.sstatus->write(s);
set_privilege(PRV_S, true);
} else if (state.prv <= PRV_S && bit < max_xlen && ((hsdeleg >> bit) & 1)) {
@@ -896,6 +914,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, state.prv);
s = set_field(s, MSTATUS_SIE, 0);
+ s = set_field(s, MSTATUS_SPELP, state.elp);
+ state.elp = elp_t::NO_LP_EXPECTED;
state.nonvirtual_sstatus->write(s);
if (extension_enabled('H')) {
s = state.hstatus->read();
@@ -927,6 +947,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
s = set_field(s, MSTATUS_MIE, 0);
s = set_field(s, MSTATUS_MPV, curr_virt);
s = set_field(s, MSTATUS_GVA, t.has_gva());
+ s = set_field(s, MSTATUS_MPELP, state.elp);
+ state.elp = elp_t::NO_LP_EXPECTED;
state.mstatus->write(s);
if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change
set_privilege(PRV_M, false);
@@ -961,6 +983,13 @@ const char* processor_t::get_symbol(uint64_t addr)
return sim->get_symbol(addr);
}
+void processor_t::execute_insn_prehook(insn_t insn)
+{
+ if (extension_enabled(EXT_ZICFILP)) {
+ zicfilp_check_if_lpad_required(state.elp, insn);
+ }
+}
+
void processor_t::disasm(insn_t insn)
{
uint64_t bits = insn.bits();
@@ -1037,6 +1066,24 @@ reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc)
throw trap_illegal_instruction(insn.bits() & 0xffffffffULL);
}
+static insn_desc_t
+propagate_instruction_in_vector(std::vector<insn_desc_t> &instructions,
+ std::vector<insn_desc_t>::iterator it) {
+ assert(it != instructions.end());
+ insn_desc_t desc = *it;
+ if (it->mask != 0 && it != instructions.begin() &&
+ std::next(it) != instructions.end()) {
+ if (it->match != std::prev(it)->match &&
+ it->match != std::next(it)->match) {
+ // move to front of opcode list to reduce miss penalty
+ while (--it >= instructions.begin())
+ *std::next(it) = *it;
+ instructions[0] = desc;
+ }
+ }
+ return desc;
+}
+
insn_func_t processor_t::decode_insn(insn_t insn)
{
// look up opcode in hash table
@@ -1047,21 +1094,18 @@ insn_func_t processor_t::decode_insn(insn_t insn)
if (unlikely(insn.bits() != desc.match)) {
// fall back to linear search
- int cnt = 0;
- insn_desc_t* p = &instructions[0];
- while ((insn.bits() & p->mask) != p->match)
- p++, cnt++;
- desc = *p;
-
- if (p->mask != 0 && p > &instructions[0]) {
- if (p->match != (p - 1)->match && p->match != (p + 1)->match) {
- // move to front of opcode list to reduce miss penalty
- while (--p >= &instructions[0])
- *(p + 1) = *p;
- instructions[0] = desc;
- }
+ auto matching = [insn_bits = insn.bits()](const insn_desc_t &d) {
+ return (insn_bits & d.mask) == d.match;
+ };
+ auto p = std::find_if(custom_instructions.begin(),
+ custom_instructions.end(), matching);
+ if (p != custom_instructions.end()) {
+ desc = propagate_instruction_in_vector(custom_instructions, p);
+ } else {
+ p = std::find_if(instructions.begin(), instructions.end(), matching);
+ assert(p != instructions.end());
+ desc = propagate_instruction_in_vector(instructions, p);
}
-
opcode_cache[idx] = desc;
opcode_cache[idx].match = insn.bits();
}
@@ -1069,12 +1113,14 @@ insn_func_t processor_t::decode_insn(insn_t insn)
return desc.func(xlen, rve, log_commits_enabled);
}
-void processor_t::register_insn(insn_desc_t desc)
-{
+void processor_t::register_insn(insn_desc_t desc, bool is_custom) {
assert(desc.fast_rv32i && desc.fast_rv64i && desc.fast_rv32e && desc.fast_rv64e &&
desc.logged_rv32i && desc.logged_rv64i && desc.logged_rv32e && desc.logged_rv64e);
- instructions.push_back(desc);
+ if (is_custom)
+ custom_instructions.push_back(desc);
+ else
+ instructions.push_back(desc);
}
void processor_t::build_opcode_map()
@@ -1086,16 +1132,17 @@ void processor_t::build_opcode_map()
return lhs.match > rhs.match;
}
};
+
std::sort(instructions.begin(), instructions.end(), cmp());
+ std::sort(custom_instructions.begin(), custom_instructions.end(), cmp());
for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
opcode_cache[i] = insn_desc_t::illegal();
}
-void processor_t::register_extension(extension_t* x)
-{
+void processor_t::register_extension(extension_t *x) {
for (auto insn : x->get_instructions())
- register_insn(insn);
+ register_custom_insn(insn);
build_opcode_map();
for (auto disasm_insn : x->get_disasms())
@@ -1131,7 +1178,7 @@ void processor_t::register_base_instructions()
extern reg_t logged_rv32e_##name(processor_t*, insn_t, reg_t); \
extern reg_t logged_rv64e_##name(processor_t*, insn_t, reg_t); \
if (name##_supported) { \
- register_insn((insn_desc_t) { \
+ register_base_insn((insn_desc_t) { \
name##_match, \
name##_mask, \
fast_rv32i_##name, \
@@ -1144,10 +1191,8 @@ void processor_t::register_base_instructions()
logged_rv64e_##name}); \
}
#include "insn_list.h"
- #undef DEFINE_INSN
-
// terminate instruction list with a catch-all
- register_insn(insn_desc_t::illegal());
+ register_base_insn(insn_desc_t::illegal());
build_opcode_map();
}
diff --git a/riscv/processor.h b/riscv/processor.h
index f9dcf25..ec42418 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -189,6 +189,8 @@ struct state_t
reg_t last_inst_priv;
int last_inst_xlen;
int last_inst_flen;
+
+ elp_t elp;
};
// this class represents one processor in a RISC-V machine.
@@ -281,7 +283,12 @@ public:
FILE *get_log_file() { return log_file; }
- void register_insn(insn_desc_t);
+ void register_base_insn(insn_desc_t insn) {
+ register_insn(insn, false /* is_custom */);
+ }
+ void register_custom_insn(insn_desc_t insn) {
+ register_insn(insn, true /* is_custom */);
+ }
void register_extension(extension_t*);
// MMIO slave interface
@@ -310,6 +317,8 @@ public:
void clear_waiting_for_interrupt() { in_wfi = false; };
bool is_waiting_for_interrupt() { return in_wfi; };
+ void execute_insn_prehook(insn_t insn);
+
private:
const isa_parser_t * const isa;
const cfg_t * const cfg;
@@ -336,6 +345,7 @@ private:
mutable std::bitset<NUM_ISA_EXTENSIONS> extension_assumed_const;
std::vector<insn_desc_t> instructions;
+ std::vector<insn_desc_t> custom_instructions;
std::unordered_map<reg_t,uint64_t> pc_histogram;
static const size_t OPCODE_CACHE_SIZE = 8191;
@@ -346,6 +356,7 @@ private:
void take_trap(trap_t& t, reg_t epc); // take an exception
void take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc, bool virt);
void disasm(insn_t insn); // disassemble and print an instruction
+ void register_insn(insn_desc_t, bool);
int paddr_bits();
void enter_debug_mode(uint8_t cause);
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 04747c9..0c4a14b 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,7 +7,7 @@ riscv_subproject_deps = \
fesvr \
softfloat \
-riscv_CFLAGS = -fPIC
+riscv_CFLAGS = -fPIC -I$(src_dir)/fdt
riscv_install_shared_lib = yes
@@ -1392,6 +1392,9 @@ riscv_insn_ext_zimop = \
mop_r_N \
mop_rr_N \
+riscv_insn_ext_zicfilp = \
+ lpad
+
riscv_insn_ext_zvk = \
$(riscv_insn_ext_zvbb) \
$(riscv_insn_ext_zvbc) \
@@ -1431,6 +1434,7 @@ riscv_insn_list = \
$(riscv_insn_smrnmi) \
$(riscv_insn_svinval) \
$(riscv_insn_ext_zimop) \
+ $(riscv_insn_ext_zicfilp) \
riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))
diff --git a/riscv/trap.h b/riscv/trap.h
index 54948fd..5eb62cf 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -119,5 +119,6 @@ DECLARE_MEM_GVA_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault)
DECLARE_MEM_GVA_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault)
DECLARE_INST_TRAP(CAUSE_VIRTUAL_INSTRUCTION, virtual_instruction)
DECLARE_MEM_GVA_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault)
+DECLARE_INST_TRAP(CAUSE_SOFTWARE_CHECK_FAULT, software_check)
#endif
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h
index b198d54..42d723a 100644
--- a/riscv/v_ext_macros.h
+++ b/riscv/v_ext_macros.h
@@ -215,8 +215,11 @@ static inline bool is_overlapped_widen(const int astart, int asize,
VI_GENERAL_LOOP_BASE \
VI_LOOP_ELEMENT_SKIP();
+#define VI_LOOP_END_BASE \
+ }
+
#define VI_LOOP_END \
- } \
+ VI_LOOP_END_BASE \
P.VU.vstart->write(0);
#define VI_LOOP_REDUCTION_END(x) \
generated by cgit v1.1 at 2024-07-17 08:09:01 +0000