aboutsummaryrefslogtreecommitdiff
path: root/riscv/riscv.ac
diff options
context:
space:
mode:
Diffstat (limited to 'riscv/riscv.ac')
-rw-r--r--riscv/riscv.ac5
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 64693e9..a43bcd6 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -45,3 +45,8 @@ AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardwa
AS_IF([test "x$enable_misaligned" = "xyes"], [
AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores])
])
+
+AC_ARG_ENABLE([dual-endian], AS_HELP_STRING([--enable-dual-endian], [Enable support for running target in either endianness]))
+AS_IF([test "x$enable_dual_endian" = "xyes"], [
+ AC_DEFINE([RISCV_ENABLE_DUAL_ENDIAN],,[Enable support for running target in either endianness])
+])