diff options
Diffstat (limited to 'riscv/insns')
48 files changed, 48 insertions, 52 deletions
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h index 3e5963d..9990174 100644 --- a/riscv/insns/fadd_d.h +++ b/riscv/insns/fadd_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2)); +WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h index a35a524..cdef36a 100644 --- a/riscv/insns/fadd_s.h +++ b/riscv/insns/fadd_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2)); +WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h index f4883ef..9456123 100644 --- a/riscv/insns/fclass_d.h +++ b/riscv/insns/fclass_d.h @@ -1,3 +1,3 @@ require_extension('D'); require_fp; -WRITE_RD(f64_classify(FRS1)); +WRITE_RD(f64_classify(f64(FRS1))); diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h index a2d5b63..a392db8 100644 --- a/riscv/insns/fclass_s.h +++ b/riscv/insns/fclass_s.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -WRITE_RD(f32_classify(FRS1)); +WRITE_RD(f32_classify(f32(FRS1))); diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h index 08716cf..fece227 100644 --- a/riscv/insns/fcvt_d_l.h +++ b/riscv/insns/fcvt_d_l.h @@ -2,5 +2,5 @@ require_extension('D'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i64_to_f64(RS1)); +WRITE_FRD(i64_to_f64(RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h index 306d7fe..775c7ae 100644 --- a/riscv/insns/fcvt_d_lu.h +++ b/riscv/insns/fcvt_d_lu.h @@ -2,5 +2,5 @@ require_extension('D'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui64_to_f64(RS1)); +WRITE_FRD(ui64_to_f64(RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h index 177e77c..ec778cc 100644 --- a/riscv/insns/fcvt_d_s.h +++ b/riscv/insns/fcvt_d_s.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_to_f64(FRS1)); +WRITE_FRD(f32_to_f64(f32(FRS1)).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h index 4c4861c..753250d 100644 --- a/riscv/insns/fcvt_d_w.h +++ b/riscv/insns/fcvt_d_w.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i32_to_f64((int32_t)RS1)); +WRITE_FRD(i32_to_f64((int32_t)RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h index 1dbf218..af893b3 100644 --- a/riscv/insns/fcvt_d_wu.h +++ b/riscv/insns/fcvt_d_wu.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f64((uint32_t)RS1)); +WRITE_FRD(ui32_to_f64((uint32_t)RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h index ee323f3..c09e6c4 100644 --- a/riscv/insns/fcvt_l_d.h +++ b/riscv/insns/fcvt_l_d.h @@ -2,5 +2,5 @@ require_extension('D'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f64_to_i64(FRS1, RM, true)); +WRITE_RD(f64_to_i64(f64(FRS1), RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h index 6079a69..267e0eb 100644 --- a/riscv/insns/fcvt_l_s.h +++ b/riscv/insns/fcvt_l_s.h @@ -2,5 +2,5 @@ require_extension('F'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f32_to_i64(FRS1, RM, true)); +WRITE_RD(f32_to_i64(f32(FRS1), RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h index b6004ea..3a02120 100644 --- a/riscv/insns/fcvt_lu_d.h +++ b/riscv/insns/fcvt_lu_d.h @@ -2,5 +2,5 @@ require_extension('D'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f64_to_ui64(FRS1, RM, true)); +WRITE_RD(f64_to_ui64(f64(FRS1), RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h index af8e1ab..94115a3 100644 --- a/riscv/insns/fcvt_lu_s.h +++ b/riscv/insns/fcvt_lu_s.h @@ -2,5 +2,5 @@ require_extension('F'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f32_to_ui64(FRS1, RM, true)); +WRITE_RD(f32_to_ui64(f32(FRS1), RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h index c1c9f0c..211bbba 100644 --- a/riscv/insns/fcvt_s_d.h +++ b/riscv/insns/fcvt_s_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_to_f32(FRS1)); +WRITE_FRD(f64_to_f32(f64(FRS1)).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h index 9abcc80..1c0581a 100644 --- a/riscv/insns/fcvt_s_l.h +++ b/riscv/insns/fcvt_s_l.h @@ -2,5 +2,5 @@ require_extension('F'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i64_to_f32(RS1)); +WRITE_FRD(i64_to_f32(RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h index 70c676e..e9bf78e 100644 --- a/riscv/insns/fcvt_s_lu.h +++ b/riscv/insns/fcvt_s_lu.h @@ -2,5 +2,5 @@ require_extension('F'); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui64_to_f32(RS1)); +WRITE_FRD(ui64_to_f32(RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h index 1ddabd8..9411cbd 100644 --- a/riscv/insns/fcvt_s_w.h +++ b/riscv/insns/fcvt_s_w.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i32_to_f32((int32_t)RS1)); +WRITE_FRD(i32_to_f32((int32_t)RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h index c1394c3..a6cf836 100644 --- a/riscv/insns/fcvt_s_wu.h +++ b/riscv/insns/fcvt_s_wu.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f32((uint32_t)RS1)); +WRITE_FRD(ui32_to_f32((uint32_t)RS1).v); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h index bac8a9b..28eb245 100644 --- a/riscv/insns/fcvt_w_d.h +++ b/riscv/insns/fcvt_w_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f64_to_i32(FRS1, RM, true))); +WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h index 81bc89f..d30f1b4 100644 --- a/riscv/insns/fcvt_w_s.h +++ b/riscv/insns/fcvt_w_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f32_to_i32(FRS1, RM, true))); +WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h index 353ae6d..5cdc004 100644 --- a/riscv/insns/fcvt_wu_d.h +++ b/riscv/insns/fcvt_wu_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true))); +WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h index 2c1ff00..034d681 100644 --- a/riscv/insns/fcvt_wu_s.h +++ b/riscv/insns/fcvt_wu_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true))); +WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h index d52ac66..d8943de 100644 --- a/riscv/insns/fdiv_d.h +++ b/riscv/insns/fdiv_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_div(FRS1, FRS2)); +WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h index cf54c57..66ac48d 100644 --- a/riscv/insns/fdiv_s.h +++ b/riscv/insns/fdiv_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_div(FRS1, FRS2)); +WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h index 43d9c1c..541ed5b 100644 --- a/riscv/insns/feq_d.h +++ b/riscv/insns/feq_d.h @@ -1,4 +1,4 @@ require_extension('D'); require_fp; -WRITE_RD(f64_eq(FRS1, FRS2)); +WRITE_RD(f64_eq(f64(FRS1), f64(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h index 7d42634..489bea6 100644 --- a/riscv/insns/feq_s.h +++ b/riscv/insns/feq_s.h @@ -1,4 +1,4 @@ require_extension('F'); require_fp; -WRITE_RD(f32_eq(FRS1, FRS2)); +WRITE_RD(f32_eq(f32(FRS1), f32(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h index 7f6a84d..419a36f 100644 --- a/riscv/insns/fle_d.h +++ b/riscv/insns/fle_d.h @@ -1,4 +1,4 @@ require_extension('D'); require_fp; -WRITE_RD(f64_le(FRS1, FRS2)); +WRITE_RD(f64_le(f64(FRS1), f64(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h index 0884c51..5c0124e 100644 --- a/riscv/insns/fle_s.h +++ b/riscv/insns/fle_s.h @@ -1,4 +1,4 @@ require_extension('F'); require_fp; -WRITE_RD(f32_le(FRS1, FRS2)); +WRITE_RD(f32_le(f32(FRS1), f32(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h index 9fda98d..7176a96 100644 --- a/riscv/insns/flt_d.h +++ b/riscv/insns/flt_d.h @@ -1,4 +1,4 @@ require_extension('D'); require_fp; -WRITE_RD(f64_lt(FRS1, FRS2)); +WRITE_RD(f64_lt(f64(FRS1), f64(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h index 830b0a0..40acc34 100644 --- a/riscv/insns/flt_s.h +++ b/riscv/insns/flt_s.h @@ -1,4 +1,4 @@ require_extension('F'); require_fp; -WRITE_RD(f32_lt(FRS1, FRS2)); +WRITE_RD(f32_lt(f32(FRS1), f32(FRS2))); set_fp_exceptions; diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h index 8605e0b..98f1cbc 100644 --- a/riscv/insns/fmadd_d.h +++ b/riscv/insns/fmadd_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3)); +WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)).v); set_fp_exceptions; diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h index 95196b7..a78ed25 100644 --- a/riscv/insns/fmadd_s.h +++ b/riscv/insns/fmadd_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3)); +WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)).v); set_fp_exceptions; diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h index eb156de..f0bea9b 100644 --- a/riscv/insns/fmax_d.h +++ b/riscv/insns/fmax_d.h @@ -1,5 +1,4 @@ require_extension('D'); require_fp; -WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ - ? FRS1 : FRS2); +WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(f64(FRS2), f64(FRS1)) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h index 215a6d1..33b2bc6 100644 --- a/riscv/insns/fmax_s.h +++ b/riscv/insns/fmax_s.h @@ -1,5 +1,4 @@ require_extension('F'); require_fp; -WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ - ? FRS1 : FRS2); +WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(f32(FRS2), f32(FRS1)) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h index 02ea681..e22b6ea 100644 --- a/riscv/insns/fmin_d.h +++ b/riscv/insns/fmin_d.h @@ -1,5 +1,4 @@ require_extension('D'); require_fp; -WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ - ? FRS1 : FRS2); +WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(f64(FRS1), f64(FRS2)) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h index cc673a0..0ebb3a8 100644 --- a/riscv/insns/fmin_s.h +++ b/riscv/insns/fmin_s.h @@ -1,5 +1,4 @@ require_extension('F'); require_fp; -WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ - ? FRS1 : FRS2); +WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(f32(FRS1), f32(FRS2)) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h index 696f822..afcea88 100644 --- a/riscv/insns/fmsub_d.h +++ b/riscv/insns/fmsub_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN)); +WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v); set_fp_exceptions; diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h index 9251277..45945da 100644 --- a/riscv/insns/fmsub_s.h +++ b/riscv/insns/fmsub_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN)); +WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v); set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h index d74c316..04e7402 100644 --- a/riscv/insns/fmul_d.h +++ b/riscv/insns/fmul_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN)); +WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h index 284aeb3..9ae7b3c 100644 --- a/riscv/insns/fmul_s.h +++ b/riscv/insns/fmul_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN)); +WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h index bed6172..d6e1f04 100644 --- a/riscv/insns/fnmadd_d.h +++ b/riscv/insns/fnmadd_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN)); +WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h index 1378ae3..0d0b2e9 100644 --- a/riscv/insns/fnmadd_s.h +++ b/riscv/insns/fnmadd_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN)); +WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h index 340090a..ee74cab 100644 --- a/riscv/insns/fnmsub_d.h +++ b/riscv/insns/fnmsub_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3)); +WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)).v); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h index 3be27d0..3e0b8ea 100644 --- a/riscv/insns/fnmsub_s.h +++ b/riscv/insns/fnmsub_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3)); +WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v); set_fp_exceptions; diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h index 812438c..45f37ce 100644 --- a/riscv/insns/fsqrt_d.h +++ b/riscv/insns/fsqrt_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_sqrt(FRS1)); +WRITE_FRD(f64_sqrt(f64(FRS1)).v); set_fp_exceptions; diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h index d77acab..f3b3956 100644 --- a/riscv/insns/fsqrt_s.h +++ b/riscv/insns/fsqrt_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_sqrt(FRS1)); +WRITE_FRD(f32_sqrt(f32(FRS1)).v); set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h index 6ffc6b3..487743e 100644 --- a/riscv/insns/fsub_d.h +++ b/riscv/insns/fsub_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN)); +WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)).v); set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h index 6a0f853..e7a7cf1 100644 --- a/riscv/insns/fsub_s.h +++ b/riscv/insns/fsub_s.h @@ -1,5 +1,5 @@ require_extension('F'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN)); +WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)).v); set_fp_exceptions; |