diff options
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 41a15b7..72ffa27 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -350,11 +350,7 @@ void processor_t::step(size_t n) state.minstret->bump(instret); - // By default, bump the MCYCLE register by the same delta. This models a - // machine where each instruction takes exactly one cycle to retire. In a - // cosimulation environment, the RTL might manually update MCYCLE - // separately. It should do that between the end of this step() and the - // start of the next one. + // Model a hart whose CPI is 1. state.mcycle->bump(instret); n -= instret; |