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| author | Andrew Waterman <andrew@sifive.com> | 2022-02-19 01:19:20 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-02-19 01:19:20 -0800 |
| commit | f2a9fbeba2c66d5823cebbebd8de42b5e36f6f9c (patch) | |
| tree | 00b5c7c23d6a0df9eb8b69ee2e6592b95928af91 /riscv/execute.cc | |
| parent | d84569bd6222fb003579781f5a5c63bc844f3384 (diff) | |
| download | riscv-isa-sim-f2a9fbeba2c66d5823cebbebd8de42b5e36f6f9c.zip riscv-isa-sim-f2a9fbeba2c66d5823cebbebd8de42b5e36f6f9c.tar.gz riscv-isa-sim-f2a9fbeba2c66d5823cebbebd8de42b5e36f6f9c.tar.bz2 | |
Make comment more germane
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 41a15b7..72ffa27 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -350,11 +350,7 @@ void processor_t::step(size_t n) state.minstret->bump(instret); - // By default, bump the MCYCLE register by the same delta. This models a - // machine where each instruction takes exactly one cycle to retire. In a - // cosimulation environment, the RTL might manually update MCYCLE - // separately. It should do that between the end of this step() and the - // start of the next one. + // Model a hart whose CPI is 1. state.mcycle->bump(instret); n -= instret; |