diff options
| -rw-r--r-- | hwacha/hwacha.cc | 1 | ||||
| -rw-r--r-- | hwacha/opcodes_hwacha_ut.h | 4 | ||||
| -rw-r--r-- | riscv/decode.h | 1 | ||||
| -rw-r--r-- | riscv/opcodes.h | 4 | ||||
| -rw-r--r-- | riscv/pcr.h | 1 | ||||
| -rw-r--r-- | riscv/rocc.cc | 1 | ||||
| -rw-r--r-- | riscv/trap.h | 1 |
7 files changed, 9 insertions, 4 deletions
diff --git a/hwacha/hwacha.cc b/hwacha/hwacha.cc index 398fa28..8caf91e 100644 --- a/hwacha/hwacha.cc +++ b/hwacha/hwacha.cc @@ -31,6 +31,7 @@ void hwacha_t::reset() static reg_t custom(processor_t* p, insn_t insn, reg_t pc) { + require_accelerator; hwacha_t* h = static_cast<hwacha_t*>(p->get_extension()); bool matched = false; reg_t npc = -1; diff --git a/hwacha/opcodes_hwacha_ut.h b/hwacha/opcodes_hwacha_ut.h index 903efc5..cca5154 100644 --- a/hwacha/opcodes_hwacha_ut.h +++ b/hwacha/opcodes_hwacha_ut.h @@ -10,7 +10,7 @@ DECLARE_INSN(ut_remuw, 0x200703b, 0xfe00707f) DECLARE_INSN(ut_fmin_d, 0xc2000053, 0xfe00707f) DECLARE_INSN(ut_amomax_d, 0xa000302f, 0xf800707f) DECLARE_INSN(ut_fmin_s, 0xc0000053, 0xfe00707f) -DECLARE_INSN(ut_slliw, 0x4000101b, 0xfe00707f) +DECLARE_INSN(ut_slliw, 0x101b, 0xfe00707f) DECLARE_INSN(ut_lb, 0x3, 0x707f) DECLARE_INSN(ut_fcvt_s_wu, 0x78000053, 0xfff0007f) DECLARE_INSN(ut_fcvt_d_l, 0x62000053, 0xfff0007f) @@ -100,7 +100,7 @@ DECLARE_INSN(ut_remu, 0x2007033, 0xfe00707f) DECLARE_INSN(ut_flw, 0x2007, 0x707f) DECLARE_INSN(ut_remw, 0x200603b, 0xfe00707f) DECLARE_INSN(ut_sltu, 0x3033, 0xfe00707f) -DECLARE_INSN(ut_slli, 0x40001013, 0xfc00707f) +DECLARE_INSN(ut_slli, 0x1013, 0xfc00707f) DECLARE_INSN(ut_amoor_w, 0x4000202f, 0xf800707f) DECLARE_INSN(ut_fld, 0x3007, 0x707f) DECLARE_INSN(ut_fsub_s, 0x8000053, 0xfe00007f) diff --git a/riscv/decode.h b/riscv/decode.h index 7cf7eac..3fc2be7 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -145,6 +145,7 @@ private: #else # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled() #endif +#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled() #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \ diff --git a/riscv/opcodes.h b/riscv/opcodes.h index 2a42554..aa2a38c 100644 --- a/riscv/opcodes.h +++ b/riscv/opcodes.h @@ -5,7 +5,7 @@ DECLARE_INSN(fmin_d, 0xc2000053, 0xfe00707f) DECLARE_INSN(amomax_d, 0xa000302f, 0xf800707f) DECLARE_INSN(bltu, 0x6063, 0x707f) DECLARE_INSN(fmin_s, 0xc0000053, 0xfe00707f) -DECLARE_INSN(slliw, 0x4000101b, 0xfe00707f) +DECLARE_INSN(slliw, 0x101b, 0xfe00707f) DECLARE_INSN(lb, 0x3, 0x707f) DECLARE_INSN(fcvt_s_wu, 0x78000053, 0xfff0007f) DECLARE_INSN(fcvt_d_l, 0x62000053, 0xfff0007f) @@ -113,7 +113,7 @@ DECLARE_INSN(remu, 0x2007033, 0xfe00707f) DECLARE_INSN(flw, 0x2007, 0x707f) DECLARE_INSN(remw, 0x200603b, 0xfe00707f) DECLARE_INSN(sltu, 0x3033, 0xfe00707f) -DECLARE_INSN(slli, 0x40001013, 0xfc00707f) +DECLARE_INSN(slli, 0x1013, 0xfc00707f) DECLARE_INSN(amoor_w, 0x4000202f, 0xf800707f) DECLARE_INSN(beq, 0x63, 0x707f) DECLARE_INSN(fld, 0x3007, 0x707f) diff --git a/riscv/pcr.h b/riscv/pcr.h index b90884b..6c6d986 100644 --- a/riscv/pcr.h +++ b/riscv/pcr.h @@ -59,6 +59,7 @@ #define CAUSE_MISALIGNED_STORE 9 #define CAUSE_FAULT_LOAD 10 #define CAUSE_FAULT_STORE 11 +#define CAUSE_ACCELERATOR_DISABLED 12 // page table entry (PTE) fields #define PTE_V 0x001 // Entry is a page Table descriptor diff --git a/riscv/rocc.cc b/riscv/rocc.cc index 7988c01..e51aee5 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -5,6 +5,7 @@ #define customX(n) \ static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ { \ + require_accelerator; \ rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \ rocc_insn_union_t u; \ u.i = insn; \ diff --git a/riscv/trap.h b/riscv/trap.h index 9a1a2f9..bd7e0ee 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -54,5 +54,6 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) +DECLARE_TRAP(12, accelerator_disabled) #endif |