diff options
| -rw-r--r-- | riscv/decode.h | 9 | ||||
| -rw-r--r-- | riscv/execute.cc | 11 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 |
3 files changed, 15 insertions, 7 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f8437ca..f4d6b6c 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -200,18 +200,21 @@ private: #define set_pc_and_serialize(x) \ do { set_pc(x); /* check alignment */ \ - npc = PC_SERIALIZE; \ + npc = PC_SERIALIZE_AFTER; \ STATE.pc = (x); \ } while(0) -#define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */ +/* Sentinel PC values to serialize simulator pipeline */ +#define PC_SERIALIZE_BEFORE 3 +#define PC_SERIALIZE_AFTER 5 +#define invalid_pc(pc) ((pc) & 1) /* Convenience wrappers to simplify softfloat code sequences */ #define f32(x) ((float32_t){(uint32_t)x}) #define f64(x) ((float64_t){(uint64_t)x}) #define validate_csr(which, write) ({ \ - if (!STATE.serialized) return PC_SERIALIZE; \ + if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ STATE.serialized = false; \ unsigned csr_priv = get_field((which), 0x300); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ diff --git a/riscv/execute.cc b/riscv/execute.cc index a2e71a1..014055b 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -43,7 +43,7 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { commit_log_stash_privilege(p->get_state()); reg_t npc = fetch.func(p, fetch.insn, pc); - if (npc != PC_SERIALIZE) { + if (!invalid_pc(npc)) { commit_log_print_insn(p->get_state(), pc, fetch.insn); p->update_histogram(pc); } @@ -59,9 +59,13 @@ void processor_t::step(size_t n) mmu_t* _mmu = mmu; #define advance_pc() \ - if (unlikely(pc == PC_SERIALIZE)) { \ + if (unlikely(invalid_pc(pc))) { \ + switch (pc) { \ + case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ + case PC_SERIALIZE_AFTER: instret++; break; \ + default: abort(); \ + } \ pc = state.pc; \ - state.serialized = true; \ break; \ } else { \ state.pc = pc; \ @@ -70,7 +74,6 @@ void processor_t::step(size_t n) try { - check_timer(); take_interrupt(); if (unlikely(debug)) diff --git a/riscv/processor.cc b/riscv/processor.cc index a79ee7b..1503661 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -161,6 +161,8 @@ static int ctz(reg_t val) void processor_t::take_interrupt() { + check_timer(); + reg_t interrupts = state.mip & state.mie; reg_t m_interrupts = interrupts & ~state.mideleg; |