diff options
| -rw-r--r-- | riscv/csrs.cc | 3 | ||||
| -rw-r--r-- | riscv/processor.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index e985db3..02a2c4f 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -412,7 +412,8 @@ reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { // If a configuration has FS bits, they will always be accessible no // matter the state of misa. const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')) && !proc->extension_enabled(EXT_ZFINX); - const bool has_vs = proc->extension_enabled('V'); + // Implementations w/o V may still have mstatus.vs, + const bool has_vs = proc->any_vector_extensions(); return 0 | (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0) | (has_page ? (SSTATUS_SUM | SSTATUS_MXR) : 0) diff --git a/riscv/processor.h b/riscv/processor.h index 9b776e2..1f11393 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -273,6 +273,9 @@ public: bool any_custom_extensions() const { return !custom_extensions.empty(); } + bool any_vector_extensions() const { + return VU.VLEN > 0; + } bool extension_enabled(unsigned char ext) const { return extension_enabled(isa_extension_t(ext)); } |