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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-11 00:26:01 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-13 07:28:10 -0800 |
| commit | ca648e6e24a8968f4e33ca1859d37a760004e953 (patch) | |
| tree | 1940751cdea57fc151ccf3d56b47d133ed08fef3 /spike_main | |
| parent | 4ac95a8c99d19c4db3be648e88f853ddf4f66d53 (diff) | |
| download | riscv-isa-sim-ca648e6e24a8968f4e33ca1859d37a760004e953.zip riscv-isa-sim-ca648e6e24a8968f4e33ca1859d37a760004e953.tar.gz riscv-isa-sim-ca648e6e24a8968f4e33ca1859d37a760004e953.tar.bz2 | |
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
1. fix disam
2. refine checking rule and move them out of loop
3. add missing exception keeping for each element
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/disasm.cc | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 373c6bb..5ecad58 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -1037,23 +1037,19 @@ disassembler_t::disassembler_t(int xlen) add_insn(new disasm_insn_t(#name ".vf", match_##name##_vf, mask_##name##_vf, \ {&vd, &vs2, &frs1, &opt, &vm})); \ - #define DISASM_VFUNARY0_INSN(name, extra, suf) \ + #define DISASM_VFUNARY0_INSN(name, suf) \ add_insn(new disasm_insn_t(#name "cvt.xu.f." #suf, \ match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ {&vd, &vs2, &opt, &vm})); \ add_insn(new disasm_insn_t(#name "cvt.x.f." #suf, \ - match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + match_##name##cvt_x_f_##suf, mask_##name##cvt_x_f_##suf, \ {&vd, &vs2, &opt, &vm})); \ add_insn(new disasm_insn_t(#name "cvt.f.xu." #suf, \ - match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + match_##name##cvt_f_xu_##suf, mask_##name##cvt_f_xu_##suf, \ {&vd, &vs2, &opt, &vm})); \ add_insn(new disasm_insn_t(#name "cvt.f.x." #suf, \ - match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + match_##name##cvt_f_x_##suf, mask_##name##cvt_f_x_##suf, \ {&vd, &vs2, &opt, &vm})); \ - if (extra) \ - add_insn(new disasm_insn_t(#name "cvt.f.f." #suf, \ - match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ - {&vd, &vs2, &opt, &vm})); \ //OPFVV/OPFVF //0b01_0000 @@ -1086,11 +1082,13 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV__F_INSN(vfrdiv); //vfunary0 - DISASM_VFUNARY0_INSN(vf, 0, v); + DISASM_VFUNARY0_INSN(vf, v); - DISASM_VFUNARY0_INSN(vfw, 1, v); + DISASM_VFUNARY0_INSN(vfw, v); + DISASM_INSN("vfwcvt.f.f.v", vfwcvt_f_f_v, 0, {&vd, &vs2, &opt, &vm}); - DISASM_VFUNARY0_INSN(vfn, 1, w); + DISASM_VFUNARY0_INSN(vfn, w); + DISASM_INSN("vfncvt.f.f.w", vfncvt_rod_f_f_w, 0, {&vd, &vs2, &opt, &vm}); DISASM_INSN("vfncvt.rod.f.f.w", vfncvt_rod_f_f_w, 0, {&vd, &vs2, &opt, &vm}); //vfunary1 |