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| author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-09 19:18:50 +0300 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-10 15:44:10 -0800 |
| commit | 28eb7aa8bece565adac4245815c80ba3fc65fc8a (patch) | |
| tree | cf1b92325453869b90314d9a293006a3bafae577 /spike_main | |
| parent | f403cb9e542155787b862d726ba334e0d0895c74 (diff) | |
| download | riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.zip riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.tar.gz riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.tar.bz2 | |
change mem_cfg_t to accept cases when (base + size) is at 64-bit address space border
Diffstat (limited to 'spike_main')
0 files changed, 0 insertions, 0 deletions