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author | YenHaoChen <howard25336284@gmail.com> | 2022-12-18 20:00:37 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-21 13:54:15 +0800 |
commit | 9f3372a8e3ee769e229328881a11a620a97495c4 (patch) | |
tree | d64c43ff8c5eca326bfe94568d895ef23a715470 /riscv/triggers.h | |
parent | 730152610adaf1828f7854eb5527b0a3f7aa5d79 (diff) | |
download | riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.zip riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.tar.gz riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.tar.bz2 |
triggers: add mcontrol6 trigger
Diffstat (limited to 'riscv/triggers.h')
-rw-r--r-- | riscv/triggers.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/triggers.h b/riscv/triggers.h index cefca51..62d6db8 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -223,6 +223,12 @@ public: virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; }; +class mcontrol6_t : public mcontrol_common_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; +}; + class module_t { public: module_t(unsigned count); |