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| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-02-13 09:03:57 -0800 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2023-02-13 09:03:57 -0800 |
| commit | 6c9b19dc1faca5e90aa9c1b0a196e98157e234b2 (patch) | |
| tree | ffb08b068334172b5a2d5483058c3b918741afcd /riscv/triggers.cc | |
| parent | e7d6aff19a071a059f1b9c2328ee4dac83bc677a (diff) | |
| download | riscv-isa-sim-6c9b19dc1faca5e90aa9c1b0a196e98157e234b2.zip riscv-isa-sim-6c9b19dc1faca5e90aa9c1b0a196e98157e234b2.tar.gz riscv-isa-sim-6c9b19dc1faca5e90aa9c1b0a196e98157e234b2.tar.bz2 | |
Defer init of type/tdata2/tdata3 until needed
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 1ba7a62..694d747 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -465,10 +465,7 @@ bool module_t::tdata1_write(unsigned index, const reg_t val) noexcept if (index > 0 && !triggers[index-1]->get_dmode() && triggers[index-1]->get_chain() && get_field(val, CSR_TDATA1_DMODE(xlen))) return false; - unsigned type = get_field(val, CSR_TDATA1_TYPE(xlen)); reg_t tdata1 = val; - reg_t tdata2 = triggers[index]->tdata2_read(proc); - reg_t tdata3 = triggers[index]->tdata3_read(proc); // hardware must zero chain in writes that set dmode to 0 if the next trigger has dmode of 1 const bool allow_chain = !(index+1 < triggers.size() && triggers[index+1]->get_dmode() && !get_field(val, CSR_TDATA1_DMODE(xlen))); @@ -481,6 +478,9 @@ bool module_t::tdata1_write(unsigned index, const reg_t val) noexcept tdata1 = set_field(tdata1, CSR_TDATA1_DMODE(xlen), 0); } + unsigned type = get_field(val, CSR_TDATA1_TYPE(xlen)); + reg_t tdata2 = triggers[index]->tdata2_read(proc); + reg_t tdata3 = triggers[index]->tdata3_read(proc); delete triggers[index]; switch (type) { case CSR_TDATA1_TYPE_MCONTROL: triggers[index] = new mcontrol_t(); break; |