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authorAndrew Waterman <andrew@sifive.com>2017-03-27 21:21:57 -0700
committerAndrew Waterman <andrew@sifive.com>2017-03-27 21:21:57 -0700
commit8f4fb411b016846a539a1ff1cd645a555e3737be (patch)
treebdd4c84e0c370f5a27aa565783d298d7a8e10396 /riscv/trap.h
parenta80c695b1961ac40086494920f82e85a085ff358 (diff)
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On EBREAK, set badaddr to pc
Diffstat (limited to 'riscv/trap.h')
-rw-r--r--riscv/trap.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/trap.h b/riscv/trap.h
index a289a68..20313e9 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -47,7 +47,7 @@ class mem_trap_t : public trap_t
DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)