diff options
| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-01-26 09:42:47 -0800 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2023-03-09 14:07:02 -0800 |
| commit | 1ffef82ac10188e45ec0cdc1e7b286b1bf40185a (patch) | |
| tree | 2d0cad40fd2cece7915a005b4a8a363c441fbf7a /riscv/simif.h | |
| parent | f01094d03b31600af97b22e8cbe83a7c8accd423 (diff) | |
| download | riscv-isa-sim-1ffef82ac10188e45ec0cdc1e7b286b1bf40185a.zip riscv-isa-sim-1ffef82ac10188e45ec0cdc1e7b286b1bf40185a.tar.gz riscv-isa-sim-1ffef82ac10188e45ec0cdc1e7b286b1bf40185a.tar.bz2 | |
Move methods used by debug_module/clint/plic up to simif_t
So we can soon convert those classes to use simif_t instead of sim_t.
Diffstat (limited to 'riscv/simif.h')
| -rw-r--r-- | riscv/simif.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/riscv/simif.h b/riscv/simif.h index c756b9c..74ddcdf 100644 --- a/riscv/simif.h +++ b/riscv/simif.h @@ -3,7 +3,11 @@ #ifndef _RISCV_SIMIF_H #define _RISCV_SIMIF_H +#include <map> #include "decode.h" +#include "cfg.h" + +class processor_t; // this is the interface to the simulator used by the processors and memory class simif_t @@ -19,10 +23,15 @@ public: // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) = 0; + virtual const cfg_t &get_cfg() const = 0; + virtual const std::map<size_t, processor_t*>& get_harts() const = 0; + virtual const char* get_symbol(uint64_t paddr) = 0; virtual ~simif_t() = default; + unsigned nprocs() const { return get_cfg().nprocs(); } + }; #endif |