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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2023-12-01 09:10:44 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-01 09:10:44 +0800 |
| commit | e9ae2287e174b67df95556266647731125307989 (patch) | |
| tree | 69e1bd3b667f071a24d57e54624dac9d0b98face /riscv/sim.h | |
| parent | 0c1397661ce383fa303bd878b2fc1172f3ad9213 (diff) | |
| download | riscv-isa-sim-e9ae2287e174b67df95556266647731125307989.zip riscv-isa-sim-e9ae2287e174b67df95556266647731125307989.tar.gz riscv-isa-sim-e9ae2287e174b67df95556266647731125307989.tar.bz2 | |
typo: vwsll.vi: fix a typo on disassembling vwsll.vi
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Diffstat (limited to 'riscv/sim.h')
0 files changed, 0 insertions, 0 deletions