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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 17:34:54 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 17:34:54 -0700 |
commit | cb6cfc5f3ad18280c6dce1f03ee4ff87e4677dad (patch) | |
tree | 2f2416b151713f95aaa0d24d7a5163330c3d0d90 /riscv/sim.cc | |
parent | 9543d241b320cb1c4982949aa6d012940c8f5377 (diff) | |
download | riscv-isa-sim-cb6cfc5f3ad18280c6dce1f03ee4ff87e4677dad.zip riscv-isa-sim-cb6cfc5f3ad18280c6dce1f03ee4ff87e4677dad.tar.gz riscv-isa-sim-cb6cfc5f3ad18280c6dce1f03ee4ff87e4677dad.tar.bz2 |
refactor disassembler, and add hwacha disassembler
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r-- | riscv/sim.cc | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index a4a1c17..4d61555 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -79,16 +79,16 @@ void sim_t::run() if (debug || ctrlc_pressed) interactive(); else - step(INTERLEAVE, false); + step(INTERLEAVE); } } -void sim_t::step(size_t n, bool noisy) +void sim_t::step(size_t n) { for (size_t i = 0, steps = 0; i < n; i += steps) { steps = std::min(n - i, INTERLEAVE - current_step); - procs[current_proc]->step(steps, noisy); + procs[current_proc]->step(steps); current_step += steps; if (current_step == INTERLEAVE) @@ -117,3 +117,14 @@ void sim_t::stop() while (htif->tick()) ; } + +void sim_t::set_debug(bool value) +{ + debug = value; +} + +void sim_t::set_procs_debug(bool value) +{ + for (size_t i=0; i< procs.size(); i++) + procs[i]->set_debug(value); +} |