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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-31 18:28:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-31 18:29:45 -0700 |
| commit | c1273bcbaf659f5bb54fb85e1292b21d70503bc4 (patch) | |
| tree | f6b49e61986ce67bf17dffdee13771a7e7f0d46d /riscv/sim.cc | |
| parent | 1f9205c93b3541b5c2ae19d4a6250aab70977e5f (diff) | |
| download | riscv-isa-sim-c1273bcbaf659f5bb54fb85e1292b21d70503bc4.zip riscv-isa-sim-c1273bcbaf659f5bb54fb85e1292b21d70503bc4.tar.gz riscv-isa-sim-c1273bcbaf659f5bb54fb85e1292b21d70503bc4.tar.bz2 | |
Use single, shared real-time counter
This required disentangling INSTRET/CYCLE from TIME.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 0fdd829..eb31f12 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -21,7 +21,7 @@ static void handle_signal(int sig) sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, const std::vector<std::string>& args) : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))), - current_step(0), current_proc(0), debug(false) + rtc(0), current_step(0), current_proc(0), debug(false) { signal(SIGINT, &handle_signal); // allocate target machine's memory, shrinking it as necessary @@ -93,8 +93,10 @@ void sim_t::step(size_t n) { current_step = 0; procs[current_proc]->yield_load_reservation(); - if (++current_proc == procs.size()) + if (++current_proc == procs.size()) { current_proc = 0; + rtc += INTERLEAVE / INSNS_PER_RTC_TICK; + } htif->tick(); } |