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| author | Elmar Melcher <elmar@dsc.ufcg.edu.br> | 2021-07-02 11:28:40 -0300 |
|---|---|---|
| committer | emelcher <elmar@dsc.ufcg.edu.br> | 2021-08-03 10:19:27 -0300 |
| commit | 810ec3fb130bcc5e06d7fe5060a02a15a9f17cd6 (patch) | |
| tree | 1c75b3cef147aeec81fde9696f3ea8d112986a90 /riscv/sim.cc | |
| parent | a5243f4520f3e9687974328f702a22c15e199596 (diff) | |
| download | riscv-isa-sim-810ec3fb130bcc5e06d7fe5060a02a15a9f17cd6.zip riscv-isa-sim-810ec3fb130bcc5e06d7fe5060a02a15a9f17cd6.tar.gz riscv-isa-sim-810ec3fb130bcc5e06d7fe5060a02a15a9f17cd6.tar.bz2 | |
activate socket comunication in simulator
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 3c37c44..d40e1f6 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -62,6 +62,11 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, debug_module(this, dm_config) { signal(SIGINT, &handle_signal); + +#ifdef HAVE_BOOST_ASIO + io_service_ptr = io_service_ptr_ctor; // socket interface + acceptor_ptr = acceptor_ptr_ctor; // socket interface +#endif sout.rdbuf(cerr.rdbuf()); // debug output goes to stderr by default for (auto& x : mems) |