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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-05-15 18:31:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-05-15 18:31:03 -0700 |
| commit | 2183afefb8f8534ff43d76ea93d7ac0b0e060fc8 (patch) | |
| tree | 43216d45251a3323b1ab24475bd7e64801e00894 /riscv/sim.cc | |
| parent | 546ceaee914e8d87fbbfdb04f5923fe002a9b9c7 (diff) | |
| download | riscv-isa-sim-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.zip riscv-isa-sim-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.tar.gz riscv-isa-sim-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.tar.bz2 | |
fix htif interaction with interactive mode
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 27933b7..8a56cd9 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -12,10 +12,9 @@ sim_t::sim_t(int _nprocs, htif_t* _htif) : htif(_htif), - tohost(0), - fromhost(0), procs(_nprocs), - running(false) + running(false), + steps(0) { // allocate target machine's memory, shrinking it as necessary // until the allocation succeeds @@ -69,7 +68,7 @@ void sim_t::run(bool debug) // word 1 of memory contains the core count mmu->store_uint32(4, num_cores()); - //htif->wait_for_start(); + htif->wait_for_start(); for(running = true; running; ) { @@ -82,8 +81,12 @@ void sim_t::run(bool debug) void sim_t::step_all(size_t n, size_t interleave, bool noisy) { - htif->wait_for_packet(); for(size_t j = 0; j < n; j+=interleave) + { + if (steps % 16384 + interleave >= 16384) + htif->wait_for_packet(); + steps += interleave; for(int i = 0; i < (int)num_cores(); i++) procs[i]->step(interleave,noisy); + } } |