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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-11-12 17:51:46 -0800
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-11-12 17:52:56 -0800
commit0c3af3d73a28c0fc57eac535b2a28f45134b556b (patch)
treea9ad7bab1842bde77d6755d96b22a45a510e7a41 /riscv/sim.cc
parenta7bde15c2b79de12484748b462e511e0d1c2eca5 (diff)
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Generate device tree for target machine
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r--riscv/sim.cc55
1 files changed, 47 insertions, 8 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc
index f7ff11d..67b655e 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -2,6 +2,7 @@
#include "sim.h"
#include "htif.h"
+#include "devicetree.h"
#include <map>
#include <iostream>
#include <climits>
@@ -43,6 +44,8 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
for (size_t i = 0; i < procs.size(); i++)
procs[i] = new processor_t(isa, this, i);
+
+ make_device_tree();
}
sim_t::~sim_t()
@@ -53,12 +56,6 @@ sim_t::~sim_t()
free(mem);
}
-void sim_t::send_ipi(reg_t who)
-{
- if (who < procs.size())
- procs[who]->deliver_ipi();
-}
-
reg_t sim_t::get_scr(int which)
{
switch (which)
@@ -146,10 +143,52 @@ void sim_t::set_procs_debug(bool value)
bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
{
- return false;
+ if (addr + len < addr)
+ return false;
+ return bus.load(addr, len, bytes);
}
bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
{
- return false;
+ if (addr + len < addr)
+ return false;
+ return bus.store(addr, len, bytes);
+}
+
+void sim_t::make_device_tree()
+{
+ char buf[32];
+ size_t max_devtree_size = procs.size() * 4096; // sloppy upper bound
+ size_t cpu_size = NCSR * procs[0]->max_xlen / 8;
+ reg_t cpu_addr = memsz + max_devtree_size;
+
+ device_tree dt;
+ dt.begin_node("");
+ dt.add_prop("#address-cells", 2);
+ dt.add_prop("#size-cells", 2);
+ dt.add_prop("model", "Spike");
+ dt.begin_node("memory@0");
+ dt.add_prop("device_type", "memory");
+ dt.add_reg({0, memsz});
+ dt.end_node();
+ dt.begin_node("cpus");
+ dt.add_prop("#address-cells", 2);
+ dt.add_prop("#size-cells", 2);
+ for (size_t i = 0; i < procs.size(); i++) {
+ sprintf(buf, "cpu@%" PRIx64, cpu_addr);
+ dt.begin_node(buf);
+ dt.add_prop("device_type", "cpu");
+ dt.add_prop("compatible", "riscv");
+ dt.add_prop("isa", procs[i]->isa);
+ dt.add_reg({cpu_addr});
+ dt.end_node();
+
+ bus.add_device(cpu_addr, procs[i]);
+ cpu_addr += cpu_size;
+ }
+ dt.end_node();
+ dt.end_node();
+
+ devicetree.reset(new rom_device_t(dt.finalize()));
+ bus.add_device(memsz, devicetree.get());
}