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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-01 14:49:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-08-01 17:13:57 -0700 |
| commit | e98294c3c2ef464e233814f1cc9ce59550dba41f (patch) | |
| tree | bd8bd9505789959319bf8beec45d711f22577be2 /riscv/riscv.mk.in | |
| parent | fdd2570fc4d93ebdc07551988fe5ccab519d281c (diff) | |
| download | riscv-isa-sim-e98294c3c2ef464e233814f1cc9ce59550dba41f.zip riscv-isa-sim-e98294c3c2ef464e233814f1cc9ce59550dba41f.tar.gz riscv-isa-sim-e98294c3c2ef464e233814f1cc9ce59550dba41f.tar.bz2 | |
Move CSR initialization to its own file
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 60723b5..bc512bf 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -68,6 +68,7 @@ riscv_srcs = \ remote_bitbang.cc \ jtag_dtm.cc \ csrs.cc \ + csr_init.cc \ triggers.cc \ vector_unit.cc \ socketif.cc \ |