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| author | Andrew Waterman <andrew@sifive.com> | 2019-10-28 11:02:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-28 11:02:56 -0700 |
| commit | 3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78 (patch) | |
| tree | cf77589a8ce193b3e388edfc2a12f0dd116eda35 /riscv/riscv.mk.in | |
| parent | 5652b9dd6298c7b61fe80bc2a508bbd3c9e5c5ef (diff) | |
| parent | b3c656629efc042c30ada9aaabb7c034f855f621 (diff) | |
| download | riscv-isa-sim-3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78.zip riscv-isa-sim-3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78.tar.gz riscv-isa-sim-3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78.tar.bz2 | |
Merge pull request #320 from zeldin/byteorder
Implement support for big-endian hosts
Diffstat (limited to 'riscv/riscv.mk.in')
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