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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-16 16:16:46 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-16 16:16:46 -0500 |
| commit | 68e4f06a69ca9101552a086c9abe5fdf6656b52a (patch) | |
| tree | 82642c285cf6bdd1916ef9292bc626bfdb6f0bf2 /riscv/riscv.ac | |
| parent | a31184c3de3fd981b4733b10554215db0e5aa85f (diff) | |
| parent | f6e4bd4df0d983749aac52473c0ed28c02dd60d5 (diff) | |
| download | riscv-isa-sim-68e4f06a69ca9101552a086c9abe5fdf6656b52a.zip riscv-isa-sim-68e4f06a69ca9101552a086c9abe5fdf6656b52a.tar.gz riscv-isa-sim-68e4f06a69ca9101552a086c9abe5fdf6656b52a.tar.bz2 | |
Merge branch 'emelcher-socket'
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 6761686..3acecc2 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -1,5 +1,13 @@ AC_LANG_CPLUSPLUS +AX_BOOST_BASE([1.53]) +AX_BOOST_ASIO +AX_BOOST_REGEX + +AC_CHECK_LIB([boost_system], [main], [], []) + +AC_CHECK_LIB([boost_regex], [main], [], []) + AC_ARG_WITH(isa, [AS_HELP_STRING([--with-isa=RV64IMAFDC], [Sets the default RISC-V ISA])], |