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| author | Ved Shanbhogue <ved@rivosinc.com> | 2023-12-30 14:20:00 -0600 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2023-12-30 14:20:00 -0600 |
| commit | da2f415bb62bec3e93b33b379d787b4262aade9f (patch) | |
| tree | b2efd01852e6bb8537a29e389ba3b41771925a14 /riscv/processor.h | |
| parent | f557404ceaf1c9a5cecf82a49e557dc5fbf4a728 (diff) | |
| download | riscv-isa-sim-da2f415bb62bec3e93b33b379d787b4262aade9f.zip riscv-isa-sim-da2f415bb62bec3e93b33b379d787b4262aade9f.tar.gz riscv-isa-sim-da2f415bb62bec3e93b33b379d787b4262aade9f.tar.bz2 | |
Add srmcfg CSR
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index a2e4286..0394e09 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -170,6 +170,8 @@ struct state_t csr_t_p stimecmp; csr_t_p vstimecmp; + csr_t_p srmcfg; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This |