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| author | Andrew Waterman <andrew@sifive.com> | 2023-02-04 17:47:47 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-02-28 15:15:41 -0800 |
| commit | 2c9b399f7bb78ae99546cbe66ae02a76218aeb49 (patch) | |
| tree | 16954d963683d0490dcdf423cf5b6743dbc2e9ac /riscv/plic.cc | |
| parent | d1ae27b7f843b35bd32778c54b4973d7aeffad52 (diff) | |
| download | riscv-isa-sim-2c9b399f7bb78ae99546cbe66ae02a76218aeb49.zip riscv-isa-sim-2c9b399f7bb78ae99546cbe66ae02a76218aeb49.tar.gz riscv-isa-sim-2c9b399f7bb78ae99546cbe66ae02a76218aeb49.tar.bz2 | |
Remove unused plic_t::procs field
Diffstat (limited to 'riscv/plic.cc')
| -rw-r--r-- | riscv/plic.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/plic.cc b/riscv/plic.cc index d0f1268..1dc3a0f 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -67,7 +67,7 @@ #define REG_SIZE 0x1000000 plic_t::plic_t(std::vector<processor_t*>& procs, bool smode, uint32_t ndev) - : procs(procs), contexts(procs.size() * (smode ? 2 : 1)), + : contexts(procs.size() * (smode ? 2 : 1)), num_ids(ndev + 1), num_ids_word(((ndev + 1) + (32 - 1)) / 32), max_prio((1UL << PLIC_PRIO_BITS) - 1) { |