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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-19 13:06:57 -0800 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-02 12:15:25 -0800 |
commit | c0c61f09d8eb21a41b5472a85abdcac62ad665d6 (patch) | |
tree | 2744a382679bb9d43db46efb2fcb8efaee901dd5 /riscv/mmu.h | |
parent | 48e4425644c9984ea73df6633f13c8ff60d44d4d (diff) | |
download | riscv-isa-sim-c0c61f09d8eb21a41b5472a85abdcac62ad665d6.zip riscv-isa-sim-c0c61f09d8eb21a41b5472a85abdcac62ad665d6.tar.gz riscv-isa-sim-c0c61f09d8eb21a41b5472a85abdcac62ad665d6.tar.bz2 |
implement PUM functionality
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index b6697cd..b9948c5 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -161,7 +161,7 @@ private: void refill_tlb(reg_t vaddr, reg_t paddr, access_type type); // perform a page table walk for a given VA; set referenced/dirty bits - reg_t walk(reg_t addr, bool supervisor, access_type type); + reg_t walk(reg_t addr, access_type type, bool supervisor, bool pum); // handle uncommon cases: TLB misses, page faults, MMIO const uint16_t* fetch_slow_path(reg_t addr); |