diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:30:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:30:22 -0700 |
| commit | a80c695b1961ac40086494920f82e85a085ff358 (patch) | |
| tree | d7c938bdfb5aa80542e8a1f9a68421ec730ca703 /riscv/mmu.h | |
| parent | 1fa2174178a5432443f114dfc059ba19c53b1fae (diff) | |
| download | riscv-isa-sim-a80c695b1961ac40086494920f82e85a085ff358.zip riscv-isa-sim-a80c695b1961ac40086494920f82e85a085ff358.tar.gz riscv-isa-sim-a80c695b1961ac40086494920f82e85a085ff358.tar.bz2 | |
Separate page faults from physical memory access exceptions
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 9365457..66454be 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -115,6 +115,9 @@ public: auto lhs = load_##type(addr); \ store_##type(addr, f(lhs)); \ return lhs; \ + } catch (trap_load_page_fault& t) { \ + /* AMO faults should be reported as store faults */ \ + throw trap_store_page_fault(t.get_badaddr()); \ } catch (trap_load_access_fault& t) { \ /* AMO faults should be reported as store faults */ \ throw trap_store_access_fault(t.get_badaddr()); \ |