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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-16 18:48:49 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 21:53:53 -0700 |
| commit | 7bdc7c2017239f0673b25be6961743763a8413c3 (patch) | |
| tree | b730cf15caa737ce8f56ba7417f277f29efc12e3 /riscv/mmu.h | |
| parent | b4add16f4923a782f79b478d980791ec1d0bee06 (diff) | |
| download | riscv-isa-sim-7bdc7c2017239f0673b25be6961743763a8413c3.zip riscv-isa-sim-7bdc7c2017239f0673b25be6961743763a8413c3.tar.gz riscv-isa-sim-7bdc7c2017239f0673b25be6961743763a8413c3.tar.bz2 | |
commitlog: fix wrong dump when exception occurs
1. store_fault_access
reorder the log and slow_path code
2. misaligned_access
reset the log buffer in the beginning rather at the end of execution to
avoid that uncompleted execution status is brought to the next
instruction
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index f73de59..b84fd4a 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -155,8 +155,8 @@ public: } \ else { \ type##_t le_val = to_le(val); \ - if (proc) WRITE_MEM(addr, val, size); \ store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&le_val); \ + if (proc) WRITE_MEM(addr, val, size); \ } \ } |