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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-20 15:27:54 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-20 15:28:47 -0800 |
| commit | 1ef875316adee8174fe2cf83317f59019d3c1aa2 (patch) | |
| tree | f72f4185597b556f87c861cab8f112afa99b45f3 /riscv/mmu.h | |
| parent | a81fbad67234777f3ff74022ada67ded08af14d4 (diff) | |
| download | riscv-isa-sim-1ef875316adee8174fe2cf83317f59019d3c1aa2.zip riscv-isa-sim-1ef875316adee8174fe2cf83317f59019d3c1aa2.tar.gz riscv-isa-sim-1ef875316adee8174fe2cf83317f59019d3c1aa2.tar.bz2 | |
Disallow access to debug memory region unless in debug mode
... as recommended, but not required, by the spec.
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index c200084..f73de59 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -339,6 +339,9 @@ private: tlb_entry_t fetch_slow_path(reg_t addr); void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes); void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes); + bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); + bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); + bool mmio_ok(reg_t addr, access_type type); reg_t translate(reg_t addr, reg_t len, access_type type); // ITLB lookup |