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| author | Andrew Waterman <andrew@sifive.com> | 2020-06-08 14:12:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-06-08 14:12:36 -0700 |
| commit | 090a083f0d6499b830622bb10d4486afa1f2b448 (patch) | |
| tree | 72ab1f980281027656a2f2b96e85c89021f7788c /riscv/mmu.h | |
| parent | 33a6eb57564c257037780ddd2691ca621c44a55b (diff) | |
| download | riscv-isa-sim-090a083f0d6499b830622bb10d4486afa1f2b448.zip riscv-isa-sim-090a083f0d6499b830622bb10d4486afa1f2b448.tar.gz riscv-isa-sim-090a083f0d6499b830622bb10d4486afa1f2b448.tar.bz2 | |
Fix priority of misaligned exceptions for store-conditional
Previously, we unintentionally prioritized access faults and page faults.
Resolves #431
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index b84fd4a..f89d139 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -222,8 +222,11 @@ public: throw trap_load_access_fault(vaddr); // disallow LR to I/O space } - inline bool check_load_reservation(reg_t vaddr) + inline bool check_load_reservation(reg_t vaddr, size_t size) { + if (vaddr & (size-1)) + throw trap_store_address_misaligned(vaddr); + reg_t paddr = translate(vaddr, 1, STORE); if (auto host_addr = sim->addr_to_mem(paddr)) return load_reservation_address == refill_tlb(vaddr, paddr, host_addr, STORE).target_offset + vaddr; |