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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-20 00:48:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-20 00:48:16 -0700 |
| commit | ee80f2851aef29f8744b5a73afe45a1927c82b37 (patch) | |
| tree | 3876cd72a36b225c8fc665e8469f5e5d49dc0081 /riscv/mmu.cc | |
| parent | 5ed1c1f9de8053ff99e3568c2ed3957da21ce0c5 (diff) | |
| download | riscv-isa-sim-ee80f2851aef29f8744b5a73afe45a1927c82b37.zip riscv-isa-sim-ee80f2851aef29f8744b5a73afe45a1927c82b37.tar.gz riscv-isa-sim-ee80f2851aef29f8744b5a73afe45a1927c82b37.tar.bz2 | |
PUM -> SUM; expose MXR to S-mode
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 06bc11b..0b28f2f 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -162,7 +162,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen bool supervisor = mode == PRV_S; - bool pum = get_field(proc->state.mstatus, MSTATUS_PUM); + bool sum = get_field(proc->state.mstatus, MSTATUS_SUM); bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR); // verify bits xlen-1:va_bits-1 are all equal @@ -188,7 +188,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) if (PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; - } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) { + } else if ((pte & PTE_U) ? supervisor && !sum : !supervisor) { break; } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { break; |