aboutsummaryrefslogtreecommitdiff
path: root/riscv/mmu.cc
diff options
context:
space:
mode:
authorAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-13 16:42:02 -0800
committerAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-13 16:42:02 -0800
commit77f281580773fe5217ae40bcf8a0f8bc05c28ded (patch)
tree79885362aa51ce842ec912ba4523f36620b1dce8 /riscv/mmu.cc
parent7f457c47b339cc7c79f56bb277ed8ed989e88ae1 (diff)
downloadriscv-isa-sim-77f281580773fe5217ae40bcf8a0f8bc05c28ded.zip
riscv-isa-sim-77f281580773fe5217ae40bcf8a0f8bc05c28ded.tar.gz
riscv-isa-sim-77f281580773fe5217ae40bcf8a0f8bc05c28ded.tar.bz2
Improve performance for branchy code
We now use a heavily unrolled loop as the software I$, which allows the host machine's branch target prediction to associate target PCs with unique-ish host PCs.
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r--riscv/mmu.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index f8efd5a..4675f75 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -16,7 +16,7 @@ mmu_t::~mmu_t()
void mmu_t::flush_icache()
{
- for (size_t i = 0; i < ICACHE_ENTRIES; i++)
+ for (size_t i = 0; i < ICACHE_SIZE; i++)
icache[i].tag = -1;
}
@@ -32,7 +32,7 @@ void mmu_t::flush_tlb()
void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
{
reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- reg_t expected_tag = addr & ~(PGSIZE-1);
+ reg_t expected_tag = addr >> PGSHIFT;
reg_t pte = walk(addr);