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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-18 17:24:04 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-18 17:24:04 -0800 |
| commit | 67cd71d9ec5087bdcfa8fda1172abc0049df8455 (patch) | |
| tree | 2f9df81c647d287abba097c8f185931d82bfe42a /riscv/mmu.cc | |
| parent | eace5599606034850e28eef63f1e00eaf8eb6d26 (diff) | |
| download | riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.zip riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.tar.gz riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.tar.bz2 | |
Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 6162fd0..06bc11b 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -197,8 +197,15 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) !((pte & PTE_R) && (pte & PTE_W))) { break; } else { + reg_t ad = PTE_A | ((type == STORE) * PTE_D); +#ifdef RISCV_ENABLE_DIRTY // set accessed and possibly dirty bits. - *(uint32_t*)ppte |= PTE_A | ((type == STORE) * PTE_D); + *(uint32_t*)ppte |= ad; +#else + // take exception if access or possibly dirty bit is not set. + if ((pte & ad) != ad) + break; +#endif // for superpage mappings, make a fake leaf PTE for the TLB's benefit. reg_t vpn = addr >> PGSHIFT; reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; |