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| author | Tim Newsome <tim@sifive.com> | 2016-04-29 13:38:59 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (patch) | |
| tree | f20df93a80f5ee78d445f57318a89ae67afdf00a /riscv/mmu.cc | |
| parent | 901541c2ec9d5b6a9321ab2bb2ef9d7c63a9e09d (diff) | |
| download | riscv-isa-sim-57ff1b6595e485b8b002238ddbd10483bbd62fb3.zip riscv-isa-sim-57ff1b6595e485b8b002238ddbd10483bbd62fb3.tar.gz riscv-isa-sim-57ff1b6595e485b8b002238ddbd10483bbd62fb3.tar.bz2 | |
Read FP registers, and general CSRs*
*) Only works if you read CSRs that actually exist.
Diffstat (limited to 'riscv/mmu.cc')
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