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| author | jameshippisley <robinson.jh@gmail.com> | 2021-03-05 18:35:38 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-05 15:35:38 -0800 |
| commit | 53d94b12bd9a7ef0d003f8b57b81f75a9e4527e6 (patch) | |
| tree | d09ba8551256c0018a49230e2edfa5ef98279f26 /riscv/mmu.cc | |
| parent | 323a93e3e47e6a6474b4883bfa157245ecfd1411 (diff) | |
| download | riscv-isa-sim-53d94b12bd9a7ef0d003f8b57b81f75a9e4527e6.zip riscv-isa-sim-53d94b12bd9a7ef0d003f8b57b81f75a9e4527e6.tar.gz riscv-isa-sim-53d94b12bd9a7ef0d003f8b57b81f75a9e4527e6.tar.bz2 | |
Don't make MPRV load/store virtual if MPV=1, MPP=3 (#666)
* Don't make MPRV load/store virtual if MPV=1, MPP=3
* Use PRV_M instead of the value "3"
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 431dd44..a394e63 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -59,7 +59,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f if (type != FETCH) { if (!proc->state.debug_mode && get_field(proc->state.mstatus, MSTATUS_MPRV)) { mode = get_field(proc->state.mstatus, MSTATUS_MPP); - if (get_field(proc->state.mstatus, MSTATUS_MPV)) + if (get_field(proc->state.mstatus, MSTATUS_MPV) && mode != PRV_M) virt = true; } if (!proc->state.debug_mode && (xlate_flags & RISCV_XLATE_VIRT)) { |