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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 00:55:58 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:36:15 -0700 |
| commit | 3035256f1a451da1dabff677e6e14b13fef7edc1 (patch) | |
| tree | 0d82dd524add0706e5113c0fd9d55daf0f044d51 /riscv/insns/vsuxe_v.h | |
| parent | f5983b39c583971b8443b9f16705cbfb1588dbf5 (diff) | |
| download | riscv-isa-sim-3035256f1a451da1dabff677e6e14b13fef7edc1.zip riscv-isa-sim-3035256f1a451da1dabff677e6e14b13fef7edc1.tar.gz riscv-isa-sim-3035256f1a451da1dabff677e6e14b13fef7edc1.tar.bz2 | |
rvv: add amo instructions
use --isa=rv64gcv_zvamo to enable it
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsuxe_v.h')
0 files changed, 0 insertions, 0 deletions