diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 11:54:33 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-12 11:54:33 -0800 |
| commit | ff81dea8593c6e51b45e7bed230a2cafd56e4caf (patch) | |
| tree | 62bd0cca8bb49199737a5d5532314cb8080d4031 /riscv/insns/vmv_s_x.h | |
| parent | 3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78 (diff) | |
| parent | c8da0f2446d1261397965e6268d117bb50004ac9 (diff) | |
| download | riscv-isa-sim-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.zip riscv-isa-sim-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.tar.gz riscv-isa-sim-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.tar.bz2 | |
Merge pull request #355 from chihminchao/rvv-0.8-2019-11
rvv-0.8-2019-11
Diffstat (limited to 'riscv/insns/vmv_s_x.h')
| -rw-r--r-- | riscv/insns/vmv_s_x.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 38b2697..948b5be 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -24,23 +24,5 @@ if (vl > 0) { break; } - const reg_t max_len = P.VU.VLEN / sew; - for (reg_t i = 1; i < max_len; ++i) { - switch(sew) { - case e8: - P.VU.elt<uint8_t>(rd_num, i) = 0; - break; - case e16: - P.VU.elt<uint16_t>(rd_num, i) = 0; - break; - case e32: - P.VU.elt<uint32_t>(rd_num, i) = 0; - break; - default: - P.VU.elt<uint64_t>(rd_num, i) = 0; - break; - } - } - vl = 0; } |