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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-28 19:08:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-28 19:08:04 -0700 |
| commit | e8125348b3d13a2e96ae389efc2a16a1e8e34ea3 (patch) | |
| tree | 4791da3758d733d64ff7bee97a340e8210a525a6 /riscv/insns/sw.h | |
| parent | 133806b398a42da859a187eebf5792eeaed9e9d1 (diff) | |
| download | riscv-isa-sim-e8125348b3d13a2e96ae389efc2a16a1e8e34ea3.zip riscv-isa-sim-e8125348b3d13a2e96ae389efc2a16a1e8e34ea3.tar.gz riscv-isa-sim-e8125348b3d13a2e96ae389efc2a16a1e8e34ea3.tar.bz2 | |
[sim,xcc] Changed instruction format to RISC-V
Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.
Diffstat (limited to 'riscv/insns/sw.h')
| -rw-r--r-- | riscv/insns/sw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h index 7e9fff8..b4e3b3d 100644 --- a/riscv/insns/sw.h +++ b/riscv/insns/sw.h @@ -1 +1 @@ -mmu.store_uint32(RS+SIMM, RT); +mmu.store_uint32(RB+SIMM, RA); |