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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
| commit | d6fce459767509249311a120fddb21c844dc9b2c (patch) | |
| tree | b54272d8ce52f773b13dd33ae94d634538ec6599 /riscv/insns/fsw.h | |
| parent | 5f494a22db29d69893db4b39f488cf67c0ac6437 (diff) | |
| download | riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.zip riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.gz riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.bz2 | |
Implement new FP encoding
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
Diffstat (limited to 'riscv/insns/fsw.h')
| -rw-r--r-- | riscv/insns/fsw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h index 3135e9b..42fc683 100644 --- a/riscv/insns/fsw.h +++ b/riscv/insns/fsw.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -MMU.store_uint32(RS1 + insn.s_imm(), FRS2); +MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v); |