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| author | Andrew Waterman <andrew@sifive.com> | 2022-08-08 20:03:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-08 20:03:50 -0700 |
| commit | c5fc01694d6db6bc275fa97126e3573c5a6b7511 (patch) | |
| tree | fccf1a44821a8e401c9f4f5c0b8f1a725b1b9710 /riscv/insns/fmsub_s.h | |
| parent | dd9bf0d3de2dccea483723f6e5f9cf8cfc2e05e1 (diff) | |
| parent | caee7f3fa508b0bf84eb3f8d60d6c9e43b0ccf61 (diff) | |
| download | riscv-isa-sim-c5fc01694d6db6bc275fa97126e3573c5a6b7511.zip riscv-isa-sim-c5fc01694d6db6bc275fa97126e3573c5a6b7511.tar.gz riscv-isa-sim-c5fc01694d6db6bc275fa97126e3573c5a6b7511.tar.bz2 | |
Merge pull request #831 from plctlab/plct-upstream-zfinx
add support for zfinx v1.0
Diffstat (limited to 'riscv/insns/fmsub_s.h')
| -rw-r--r-- | riscv/insns/fmsub_s.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h index d46c887..179cc2f 100644 --- a/riscv/insns/fmsub_s.h +++ b/riscv/insns/fmsub_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN))); +WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); set_fp_exceptions; |