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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 21:09:14 -0700 |
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| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 21:09:14 -0700 |
| commit | 6b5af53e2b6d77ed2e6d1b437d397852fe29eb30 (patch) | |
| tree | cf364ea5aa27f87816780ec341d8cf388969361e /riscv/insns/dmtc1.h | |
| parent | 5ff63bcd7935cad840fd25844dfb590010bd2e12 (diff) | |
| download | riscv-isa-sim-6b5af53e2b6d77ed2e6d1b437d397852fe29eb30.zip riscv-isa-sim-6b5af53e2b6d77ed2e6d1b437d397852fe29eb30.tar.gz riscv-isa-sim-6b5af53e2b6d77ed2e6d1b437d397852fe29eb30.tar.bz2 | |
[sim,xcc] removed sll32/srl32/sra32 opcodes
These instructions handled static shift amounts >= 32. Since we have
a 6-bit shift amount field, these opcodes are no longer necessary.
Diffstat (limited to 'riscv/insns/dmtc1.h')
0 files changed, 0 insertions, 0 deletions