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| author | Andrew Waterman <andrew@sifive.com> | 2024-06-11 16:11:35 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-11 16:11:35 -0700 |
| commit | 9e6253f8b13bfd0ded2ececd8b0ac23902e0eac7 (patch) | |
| tree | f5eee62557aa3731bf0bca7deda761a4f228a269 /riscv/insns/c_sdsp.h | |
| parent | 9bcda41ef2ef91a29e78e2955f9bbe8c510a73b8 (diff) | |
| parent | 40b660af4d32454e6625cba0147f90a402a1a72c (diff) | |
| download | riscv-isa-sim-9e6253f8b13bfd0ded2ececd8b0ac23902e0eac7.zip riscv-isa-sim-9e6253f8b13bfd0ded2ececd8b0ac23902e0eac7.tar.gz riscv-isa-sim-9e6253f8b13bfd0ded2ececd8b0ac23902e0eac7.tar.bz2 | |
Merge pull request #1687 from riscv-software-src/flw-overlap
Separate RV32 and RV64 C instructions into separate files
Diffstat (limited to 'riscv/insns/c_sdsp.h')
| -rw-r--r-- | riscv/insns/c_sdsp.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h new file mode 100644 index 0000000..f7b8a28 --- /dev/null +++ b/riscv/insns/c_sdsp.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); |