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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 04:15:57 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 04:15:57 -0700 |
commit | 5a97139eeecac32b8127393be7fcdb23a8e98ff6 (patch) | |
tree | 610f3be4d6d45ddc02f7df9f6cc0545094b0f79f /riscv/insns/c_fsw.h | |
parent | 0de1489e8ab4a527fbcb1440a8fd5b2d4c8c9260 (diff) | |
download | riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.zip riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.tar.gz riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.tar.bz2 |
Rip out RVC for now
Diffstat (limited to 'riscv/insns/c_fsw.h')
-rw-r--r-- | riscv/insns/c_fsw.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h deleted file mode 100644 index 1d21629..0000000 --- a/riscv/insns/c_fsw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_fp; -mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S); |